Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c11a33c1 authored by Maxime Ripard's avatar Maxime Ripard Committed by Linus Walleij
Browse files

pinctrl: sunxi: Declare the interrupt function for the A31 



The primary pinctrl device has 4 interrupt banks. As usual, to be able to
generate interrupts, the pins supporting it need to be muxed to a special
function. Declare these functions in the pins array.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 8966ada2

drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c

+144 −72
Original line number Diff line number Diff line
@@ -24,208 +24,244 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { 
		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD0 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D0 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* DTR */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* DTR */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PA_EINT0 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD1 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D1 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* DSR */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* DSR */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PA_EINT1 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD2 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D2 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* DCD */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* DCD */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PA_EINT2 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD3 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D3 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* RING */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* RING */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PA_EINT3 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD4 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D4 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* TX */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* TX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PA_EINT4 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD5 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D5 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* RX */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* RX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PA_EINT5 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD6 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D6 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* RTS */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PA_EINT6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXD7 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D7 */

		  SUNXI_FUNCTION(0x4, "uart1")),	/* CTS */

		  SUNXI_FUNCTION(0x4, "uart1"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PA_EINT7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXCLK */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* D8 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D8 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PA_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXEN */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D9 */

		  SUNXI_FUNCTION(0x4, "mmc3"),		/* CMD */

		  SUNXI_FUNCTION(0x5, "mmc2")),		/* CMD */

		  SUNXI_FUNCTION(0x5, "mmc2"),		/* CMD */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PA_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* GTXCLK */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D10 */

		  SUNXI_FUNCTION(0x4, "mmc3"),		/* CLK */

		  SUNXI_FUNCTION(0x5, "mmc2")),		/* CLK */

		  SUNXI_FUNCTION(0x5, "mmc2"),		/* CLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PA_EINT10 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD0 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D11 */

		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D0 */

		  SUNXI_FUNCTION(0x5, "mmc2")),		/* D0 */

		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D0 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PA_EINT11 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD1 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D12 */

		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D1 */

		  SUNXI_FUNCTION(0x5, "mmc2")),		/* D1 */

		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D1 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PA_EINT12 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD2 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D13 */

		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D2 */

		  SUNXI_FUNCTION(0x5, "mmc2")),		/* D2 */

		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D2 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),	/* PA_EINT13 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD3 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D14 */

		  SUNXI_FUNCTION(0x4, "mmc3"),		/* D3 */

		  SUNXI_FUNCTION(0x5, "mmc2")),		/* D3 */

		  SUNXI_FUNCTION(0x5, "mmc2"),		/* D3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),	/* PA_EINT14 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD4 */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* D15 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D15 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),	/* PA_EINT15 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD5 */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* D16 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D16 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),	/* PA_EINT16 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD6 */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* D17 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D17 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),	/* PA_EINT17 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXD7 */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* D18 */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D18 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),	/* PA_EINT18 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXDV */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D19 */

		  SUNXI_FUNCTION(0x4, "pwm3")),		/* Positive */

		  SUNXI_FUNCTION(0x4, "pwm3"),		/* Positive */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),	/* PA_EINT19 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXCLK */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D20 */

		  SUNXI_FUNCTION(0x4, "pwm3")),		/* Negative */

		  SUNXI_FUNCTION(0x4, "pwm3"),		/* Negative */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),	/* PA_EINT20 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* TXERR */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D21 */

		  SUNXI_FUNCTION(0x4, "spi3")),		/* CS0 */

		  SUNXI_FUNCTION(0x4, "spi3"),		/* CS0 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),	/* PA_EINT21 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* RXERR */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D22 */

		  SUNXI_FUNCTION(0x4, "spi3")),		/* CLK */

		  SUNXI_FUNCTION(0x4, "spi3"),		/* CLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)),	/* PA_EINT22 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* COL */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* D23 */

		  SUNXI_FUNCTION(0x4, "spi3")),		/* MOSI */

		  SUNXI_FUNCTION(0x4, "spi3"),		/* MOSI */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)),	/* PA_EINT23 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* CRS */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* CLK */

		  SUNXI_FUNCTION(0x4, "spi3")),		/* MISO */

		  SUNXI_FUNCTION(0x4, "spi3"),		/* MISO */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)),	/* PA_EINT24 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* CLKIN */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* DE */

		  SUNXI_FUNCTION(0x4, "spi3")),		/* CS1 */

		  SUNXI_FUNCTION(0x4, "spi3"),		/* CS1 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)),	/* PA_EINT25 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* MDC */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* HSYNC */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* HSYNC */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)),	/* PA_EINT26 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "gmac"),		/* MDIO */

		  SUNXI_FUNCTION(0x3, "lcd1")),		/* VSYNC */

		  SUNXI_FUNCTION(0x3, "lcd1"),		/* VSYNC */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)),	/* PA_EINT27 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* MCLK */

		  SUNXI_FUNCTION(0x3, "uart3"),		/* CTS */

		  SUNXI_FUNCTION(0x4, "csi")),		/* MCLK1 */

		  SUNXI_FUNCTION(0x4, "csi"),		/* MCLK1 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* PB_EINT0 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0")),		/* BCLK */

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* BCLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* PB_EINT1 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0")),		/* LRCK */

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* LRCK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* PB_EINT2 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0")),		/* DO0 */

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO0 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* PB_EINT3 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO1 */

		  SUNXI_FUNCTION(0x3, "uart3")),	/* RTS */

		  SUNXI_FUNCTION(0x3, "uart3"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* PB_EINT4 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO2 */

		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */

		  SUNXI_FUNCTION(0x4, "i2c3")),		/* SCK */

		  SUNXI_FUNCTION(0x4, "i2c3"),		/* SCK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* PB_EINT5 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DO3 */

		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */

		  SUNXI_FUNCTION(0x4, "i2c3")),		/* SDA */

		  SUNXI_FUNCTION(0x4, "i2c3"),		/* SDA */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* PB_EINT6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x3, "i2s0")),		/* DI */

		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DI */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* PB_EINT7 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),

		  SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -510,86 +546,103 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { 
		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* PCLK */

		  SUNXI_FUNCTION(0x3, "ts")),		/* CLK */

		  SUNXI_FUNCTION(0x3, "ts"),		/* CLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),	/* PE_EINT0 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* MCLK */

		  SUNXI_FUNCTION(0x3, "ts")),		/* ERR */

		  SUNXI_FUNCTION(0x3, "ts"),		/* ERR */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* PE_EINT1 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* HSYNC */

		  SUNXI_FUNCTION(0x3, "ts")),		/* SYNC */

		  SUNXI_FUNCTION(0x3, "ts"),		/* SYNC */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),	/* PE_EINT2 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* VSYNC */

		  SUNXI_FUNCTION(0x3, "ts")),		/* DVLD */

		  SUNXI_FUNCTION(0x3, "ts"),		/* DVLD */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),	/* PE_EINT3 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D0 */

		  SUNXI_FUNCTION(0x3, "uart5")),	/* TX */

		  SUNXI_FUNCTION(0x3, "uart5"),		/* TX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),	/* PE_EINT4 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D1 */

		  SUNXI_FUNCTION(0x3, "uart5")),	/* RX */

		  SUNXI_FUNCTION(0x3, "uart5"),		/* RX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),	/* PE_EINT5 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D2 */

		  SUNXI_FUNCTION(0x3, "uart5")),	/* RTS */

		  SUNXI_FUNCTION(0x3, "uart5"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),	/* PE_EINT6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D3 */

		  SUNXI_FUNCTION(0x3, "uart5")),	/* CTS */

		  SUNXI_FUNCTION(0x3, "uart5"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),	/* PE_EINT7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D4 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D0 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D0 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),	/* PE_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D5 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D1 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D1 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),	/* PE_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D6 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D2 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D2 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),	/* PE_EINT10 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D7 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D3 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),	/* PE_EINT11 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D8 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D4 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D4 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),	/* PE_EINT12 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D9 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D5 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D5 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),	/* PE_EINT13 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D10 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D6 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D6 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),	/* PE_EINT14 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi"),		/* D11 */

		  SUNXI_FUNCTION(0x3, "ts")),		/* D7 */

		  SUNXI_FUNCTION(0x3, "ts"),		/* D7 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),	/* PE_EINT15 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "csi")),		/* MIPI CSI MCLK */

		  SUNXI_FUNCTION(0x2, "csi"),		/* MIPI CSI MCLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),	/* PE_EINT16 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),

		  SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -625,86 +678,105 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc1")),		/* CLK */

		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),	/* PG_EINT0 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc1")),		/* CMD */

		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),	/* PG_EINT1 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc1")),		/* D0 */

		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),	/* PG_EINT2 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc1")),		/* D1 */

		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),	/* PG_EINT3 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc1")),		/* D2 */

		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),	/* PG_EINT4 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc1")),		/* D3 */

		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),	/* PG_EINT5 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2")),	/* TX */

		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),	/* PG_EINT6 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2")),	/* RX */

		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),	/* PG_EINT7 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2")),	/* RTS */

		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),	/* PG_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2")),	/* CTS */

		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),	/* PG_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2c3"),		/* SCK */

		  SUNXI_FUNCTION(0x3, "usb")),		/* DP3 */

		  SUNXI_FUNCTION(0x3, "usb"),		/* DP3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)),	/* PG_EINT10 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "i2c3"),		/* SDA */

		  SUNXI_FUNCTION(0x3, "usb")),		/* DM3 */

		  SUNXI_FUNCTION(0x3, "usb"),		/* DM3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)),	/* PG_EINT11 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS1 */

		  SUNXI_FUNCTION(0x3, "i2s1")),		/* MCLK */

		  SUNXI_FUNCTION(0x3, "i2s1"),		/* MCLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)),	/* PG_EINT12 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */

		  SUNXI_FUNCTION(0x3, "i2s1")),		/* BCLK */

		  SUNXI_FUNCTION(0x3, "i2s1"),		/* BCLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)),	/* PG_EINT13 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */

		  SUNXI_FUNCTION(0x3, "i2s1")),		/* LRCK */

		  SUNXI_FUNCTION(0x3, "i2s1"),		/* LRCK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)),	/* PG_EINT14 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */

		  SUNXI_FUNCTION(0x3, "i2s1")),		/* DIN */

		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DIN */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)),	/* PG_EINT15 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */

		  SUNXI_FUNCTION(0x3, "i2s1")),		/* DOUT */

		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DOUT */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)),	/* PG_EINT16 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart4")),	/* TX */

		  SUNXI_FUNCTION(0x2, "uart4"),		/* TX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)),	/* PG_EINT17 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart4")),	/* RX */

		  SUNXI_FUNCTION(0x2, "uart4"),		/* RX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)),	/* PG_EINT18 */

	/* Hole */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),

		  SUNXI_FUNCTION(0x0, "gpio_in"),