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Commit c09513cf authored by Jordan Crouse's avatar Jordan Crouse Committed by Rob Clark
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drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter 



Even though the default countable for CP0 is CP_ALWAYS_COUNT (0),
program the selector during HW initialization in an effort to be
up front about which counters are programmed and why.

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent f56d9df6

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+3 −0
Original line number Diff line number Diff line
@@ -597,6 +597,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	/* Turn on performance counters */

	gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01);



	/* Select CP0 to always count cycles */

	gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);



	/* Increase VFD cache access so LRZ and other data gets evicted less */

	gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);