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Commit c021bf1e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm-intel 

Pull intel drm fixes from Jani Nikula:
 "Almost all of it is regression fixes all around, with cc: stable, and
  then there's Ander's fix for one of the warnings you reported.  We're
  still working on the rest"

[ Dave is on vacation, and Jani is heading out on vacation too ]

* tag 'drm-intel-next-fixes-2015-07-02' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel()
  drm/i915: fix backlight after resume on 855gm
  agp/intel: Fix typo in needs_ilk_vtd_wa()
  drm/i915/ppgtt: Break loop in gen8_ppgtt_clear_range failure path
  drm/i915: Fix IPS related flicker
parents 0c76c6ba ee46f3c7

drivers/char/agp/intel-gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -581,7 +581,7 @@ static inline int needs_ilk_vtd_wa(void) 
	/* Query intel_iommu to see if we need the workaround. Presumably that

	 * was loaded first.

	 */

	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||

	if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG ||

	     gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&

	     intel_iommu_gfx_mapped)

		return 1;

drivers/gpu/drm/i915/i915_gem_gtt.c

+3 −3
Original line number Diff line number Diff line
@@ -516,17 +516,17 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm, 
		struct page *page_table;



		if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))

			continue;

			break;



		pd = ppgtt->pdp.page_directory[pdpe];



		if (WARN_ON(!pd->page_table[pde]))

			continue;

			break;



		pt = pd->page_table[pde];



		if (WARN_ON(!pt->page))

			continue;

			break;



		page_table = pt->page;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3491,6 +3491,7 @@ enum skl_disp_power_wells { 
#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */



#define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)

#define  BLM_HISTOGRAM_ENABLE			(1 << 31)



/* New registers for PCH-split platforms. Safe where new bits show up, the

 * register layout machtes with gen4 BLC_PWM_CTL[12]. */

drivers/gpu/drm/i915/intel_display.c

+13 −0
Original line number Diff line number Diff line
@@ -13303,6 +13303,16 @@ intel_check_primary_plane(struct drm_plane *plane, 
				intel_crtc->atomic.wait_vblank = true;

		}



		/*

		 * FIXME: Actually if we will still have any other plane enabled

		 * on the pipe we could let IPS enabled still, but for

		 * now lets consider that when we make primary invisible

		 * by setting DSPCNTR to 0 on update_primary_plane function

		 * IPS needs to be disable.

		 */

		if (!state->visible || !fb)

			intel_crtc->atomic.disable_ips = true;



		intel_crtc->atomic.fb_bits |=

			INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
@@ -13400,6 +13410,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc) 
	if (intel_crtc->atomic.disable_fbc)

		intel_fbc_disable(dev);



	if (intel_crtc->atomic.disable_ips)

		hsw_disable_ips(intel_crtc);



	if (intel_crtc->atomic.pre_disable_primary)

		intel_pre_disable_primary(crtc);

drivers/gpu/drm/i915/intel_dp.c

+3 −0
Original line number Diff line number Diff line
@@ -1140,6 +1140,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) 
static void

hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)

{

	memset(&pipe_config->dpll_hw_state, 0,

	       sizeof(pipe_config->dpll_hw_state));



	switch (link_bw) {

	case DP_LINK_BW_1_62:

		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;