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Commit bfd5be0f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Misc fixes and cleanups for 4.10. Highlights:
- Cursor fixes for radeon and amdgpu
- DPM fixes for some new SI variants
- Powerplay fixes
- Clock and powergating fixes

* 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (39 commits)
  drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well
  drm/amdgpu: use pin rather than pin_restricted in a few cases
  drm/amd/powerplay: use pr_debug to print function not implemented message
  drm/amd/amdgpu: Add gpr reading for GFX v7
  drm/amd/amdgpu: Add gpr reading for GFX v6
  drm/amd/amdgpu: Add debugfs support for reading GPRs (v2)
  drm/amd/amdgpu: export vbios information (v2)
  drm/amd/amdgpu: stored bios_size
  drm/amdgpu: update golden setting of tonga
  drm/amdgpu/si: load the proper firmware on 0x87 oland boards
  drm/amdgpu: add additional pci revision to dpm workaround
  drm/radeon/si: load the proper firmware on 0x87 oland boards
  drm/radeon: add additional pci revision to dpm workaround
  drm/amd/powerplay: Fix potential NULL pointer issue
  drm/amdgpu: Don't touch GFX hw during HW fini
  drm/amd/powerplay: Adjust the position of data size initial
  drm/amd/powerplay: Ignore smu buffer usage
  drm/amd/powerplay: cut digest part
  drm/amdgpu: drop redundant vi_mqd define
  drm/amdgpu: fix gtt available page num accounting
  ...
parents 6f218909 32859f73

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+3 −2
Original line number Diff line number Diff line
@@ -842,6 +842,8 @@ struct amdgpu_gfx_funcs { 
	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);

	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);

	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);

	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);

};



struct amdgpu_gfx {
@@ -1330,6 +1332,7 @@ struct amdgpu_device { 


	/* BIOS */

	uint8_t				*bios;

	uint32_t			bios_size;

	bool				is_atom_bios;

	struct amdgpu_bo		*stollen_vga_memory;

	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
@@ -1679,8 +1682,6 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);

void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);

void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);

u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);

int amdgpu_ttm_global_init(struct amdgpu_device *adev);

int amdgpu_ttm_init(struct amdgpu_device *adev);

void amdgpu_ttm_fini(struct amdgpu_device *adev);

void amdgpu_program_register_sequence(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

+6 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) 
		iounmap(bios);

		return false;

	}

	adev->bios_size = size;

	memcpy_fromio(adev->bios, bios, size);

	iounmap(bios);

	return true;
@@ -103,6 +104,7 @@ bool amdgpu_read_bios(struct amdgpu_device *adev) 
		pci_unmap_rom(adev->pdev, bios);

		return false;

	}

	adev->bios_size = size;

	memcpy_fromio(adev->bios, bios, size);

	pci_unmap_rom(adev->pdev, bios);

	return true;
@@ -135,6 +137,7 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev) 
		DRM_ERROR("no memory to allocate for BIOS\n");

		return false;

	}

	adev->bios_size = len;



	/* read complete BIOS */

	return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);
@@ -159,6 +162,7 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev) 
	if (adev->bios == NULL) {

		return false;

	}

	adev->bios_size = size;



	return true;

}
@@ -273,6 +277,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) 
		kfree(adev->bios);

		return false;

	}

	adev->bios_size = size;

	return true;

}

#else
@@ -334,6 +339,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) 
	}



	adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);

	adev->bios_size = vhdr->ImageLength;

	ret = !!adev->bios;



out_unmap:

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+4 −2
Original line number Diff line number Diff line
@@ -723,7 +723,7 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, 
					enum cgs_ucode_id type)

{

	CGS_FUNC_ADEV;

	uint16_t fw_version;

	uint16_t fw_version = 0;



	switch (type) {

		case CGS_UCODE_ID_SDMA0:
@@ -753,9 +753,11 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, 
		case CGS_UCODE_ID_RLC_G:

			fw_version = adev->gfx.rlc_fw_version;

			break;

		case CGS_UCODE_ID_STORAGE:

			break;

		default:

			DRM_ERROR("firmware type %d do not have version\n", type);

			fw_version = 0;

			break;

	}

	return fw_version;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) 
		return r;



	if (bo->shadow)

		r = amdgpu_cs_bo_validate(p, bo);

		r = amdgpu_cs_bo_validate(p, bo->shadow);



	return r;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+80 −7
Original line number Diff line number Diff line
@@ -1470,6 +1470,9 @@ static int amdgpu_fini(struct amdgpu_device *adev) 
			amdgpu_wb_fini(adev);

			amdgpu_vram_scratch_fini(adev);

		}



		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&

			adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {

			/* ungate blocks before hw fini so that we can shutdown the blocks safely */

			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,

										     AMD_CG_STATE_UNGATE);
@@ -1478,12 +1481,15 @@ static int amdgpu_fini(struct amdgpu_device *adev) 
					  adev->ip_blocks[i].version->funcs->name, r);

				return r;

			}

		}



		r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);

		/* XXX handle errors */

		if (r) {

			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",

				  adev->ip_blocks[i].version->funcs->name, r);

		}



		adev->ip_blocks[i].status.hw = false;

	}
@@ -2979,6 +2985,66 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, 
	return result;

}



static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,

					size_t size, loff_t *pos)

{

	struct amdgpu_device *adev = f->f_inode->i_private;

	int r;

	ssize_t result = 0;

	uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;



	if (size & 3 || *pos & 3)

		return -EINVAL;



	/* decode offset */

	offset = (*pos & 0xFFF);       /* in dwords */

	se = ((*pos >> 12) & 0xFF);

	sh = ((*pos >> 20) & 0xFF);

	cu = ((*pos >> 28) & 0xFF);

	wave = ((*pos >> 36) & 0xFF);

	simd = ((*pos >> 44) & 0xFF);

	thread = ((*pos >> 52) & 0xFF);

	bank = ((*pos >> 60) & 1);



	data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);

	if (!data)

		return -ENOMEM;



	/* switch to the specific se/sh/cu */

	mutex_lock(&adev->grbm_idx_mutex);

	amdgpu_gfx_select_se_sh(adev, se, sh, cu);



	if (bank == 0) {

		if (adev->gfx.funcs->read_wave_vgprs)

			adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);

	} else {

		if (adev->gfx.funcs->read_wave_sgprs)

			adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);

	}



	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);

	mutex_unlock(&adev->grbm_idx_mutex);



	while (size) {

		uint32_t value;



		value = data[offset++];

		r = put_user(value, (uint32_t *)buf);

		if (r) {

			result = r;

			goto err;

		}



		result += 4;

		buf += 4;

		size -= 4;

	}



err:

	kfree(data);

	return result;

}



static const struct file_operations amdgpu_debugfs_regs_fops = {

	.owner = THIS_MODULE,

	.read = amdgpu_debugfs_regs_read,
@@ -3021,6 +3087,11 @@ static const struct file_operations amdgpu_debugfs_wave_fops = { 
	.read = amdgpu_debugfs_wave_read,

	.llseek = default_llseek

};

static const struct file_operations amdgpu_debugfs_gpr_fops = {

	.owner = THIS_MODULE,

	.read = amdgpu_debugfs_gpr_read,

	.llseek = default_llseek

};



static const struct file_operations *debugfs_regs[] = {

	&amdgpu_debugfs_regs_fops,
@@ -3030,6 +3101,7 @@ static const struct file_operations *debugfs_regs[] = { 
	&amdgpu_debugfs_gca_config_fops,

	&amdgpu_debugfs_sensors_fops,

	&amdgpu_debugfs_wave_fops,

	&amdgpu_debugfs_gpr_fops,

};



static const char *debugfs_regs_names[] = {
@@ -3040,6 +3112,7 @@ static const char *debugfs_regs_names[] = { 
	"amdgpu_gca_config",

	"amdgpu_sensors",

	"amdgpu_wave",

	"amdgpu_gpr",

};



static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)