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Commit bf6fc0a2 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm64-dt2-for-v4.7' of... 

Merge tag 'renesas-arm64-dt2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Merge "Second Round of Renesas ARM64 Based SoC DT Updates for v4.7" from Simon Horman:

* Don't disable referenced optional clocks in DT of r8a7795 SoC
* Populate EXTALR in DT of salvator-x board
* Enable PCIe in DT of salvator-x board

* tag 'renesas-arm64-dt2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: Don't disable referenced optional clocks
  arm64: dts: salvator-x: populate EXTALR
  arm64: dts: r8a7795: enable PCIe on Salvator-X
  arm64: dts: r8a7795: Add PCIe nodes
  arm64: dts: r8a7795: Use USB3.0 fallback compatibility string
  arm64: dts: r8a7795: Add CAN support
  arm64: dts: r8a7795: Add CAN external clock support
parents fb89cf36 9f33a8a9

arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts

+17 −0
Original line number Diff line number Diff line
@@ -141,6 +141,10 @@ 
	clock-frequency = <16666666>;

};



&extalr_clk {

	clock-frequency = <32768>;

};



&pfc {

	pinctrl-0 = <&scif_clk_pins>;

	pinctrl-names = "default";
@@ -388,3 +392,16 @@ 
&ohci2 {

	status = "okay";

};



&pcie_bus_clk {

	clock-frequency = <100000000>;

	status = "okay";

};



&pciec0 {

	status = "okay";

};



&pciec1 {

	status = "okay";

};

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+95 −3
Original line number Diff line number Diff line
@@ -115,12 +115,25 @@ 
		clock-frequency = <0>;

	};



	/* External CAN clock - to be overridden by boards that provide it */

	can_clk: can {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	/* External SCIF clock - to be overridden by boards that provide it */

	scif_clk: scif {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

		status = "disabled";

	};



	/* External PCIe clock - can be overridden by the board */

	pcie_bus_clk: pcie_bus {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	soc {
@@ -515,6 +528,36 @@ 
			#size-cells = <0>;

		};



		can0: can@e6c30000 {

			compatible = "renesas,can-r8a7795",

				     "renesas,rcar-gen3-can";

			reg = <0 0xe6c30000 0 0x1000>;

			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 916>,

			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,

			       <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		can1: can@e6c38000 {

			compatible = "renesas,can-r8a7795",

				     "renesas,rcar-gen3-can";

			reg = <0 0xe6c38000 0 0x1000>;

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 915>,

			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,

			       <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;

			assigned-clock-rates = <40000000>;

			power-domains = <&cpg>;

			status = "disabled";

		};



		hscif0: serial@e6540000 {

			compatible = "renesas,hscif-r8a7795",

				     "renesas,rcar-gen3-hscif",
@@ -944,7 +987,7 @@ 
		};



		xhci0: usb@ee000000 {

			compatible = "renesas,xhci-r8a7795";

			compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";

			reg = <0 0xee000000 0 0xc00>;

			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 328>;
@@ -953,7 +996,7 @@ 
		};



		xhci1: usb@ee0400000 {

			compatible = "renesas,xhci-r8a7795";

			compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";

			reg = <0 0xee040000 0 0xc00>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 327>;
@@ -1118,5 +1161,54 @@ 
			power-domains = <&cpg>;

			status = "disabled";

		};

		pciec0: pcie@fe000000 {

			compatible = "renesas,pcie-r8a7795";

			reg = <0 0xfe000000 0 0x80000>;

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000

				0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000

				0x02000000 0 0x30000000 0 0x30000000 0 0x08000000

				0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&cpg>;

			status = "disabled";

		};



		pciec1: pcie@ee800000 {

			compatible = "renesas,pcie-r8a7795";

			reg = <0 0xee800000 0 0x80000>;

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000

				0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000

				0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000

				0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&cpg>;

			status = "disabled";

		};

	};

};