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Commit bf3a00f8 authored by Paul Mundt's avatar Paul Mundt Committed by Linus Torvalds
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[PATCH] sh: IRQ handler updates 



This moves the various IRQ controller drivers into a new subdirectory, and
also extends the INTC2 IRQ handler to also deal with SH7760 and SH7780
interrupts, rather than just ST-40.

The old CONFIG_SH_GENERIC has also been removed from the IRQ definitions, as
new ports are expected to be based off of CONFIG_SH_UNKNOWN.  Since there are
plenty of incompatible machvecs, CONFIG_SH_GENERIC doesn't make sense anymore.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 9d44190e

arch/sh/kernel/cpu/Makefile

+3 −6
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
# Makefile for the Linux/SuperH CPU-specifc backends.

#



obj-y	:= irq_ipr.o irq_imask.o init.o bus.o

obj-y	+= irq/ init.o bus.o clock.o



obj-$(CONFIG_CPU_SH2)		+= sh2/

obj-$(CONFIG_CPU_SH3)		+= sh3/
@@ -11,6 +11,3 @@ obj-$(CONFIG_CPU_SH4) += sh4/ 
obj-$(CONFIG_SH_RTC)		+= rtc.o

obj-$(CONFIG_UBC_WAKEUP)	+= ubc.o

obj-$(CONFIG_SH_ADC)		+= adc.o
 


USE_STANDARD_AS_RULE := true

arch/sh/kernel/cpu/irq/Makefile

0 → 100644
+7 −0
Original line number Diff line number Diff line 
#

# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.

#

obj-y	+= ipr.o imask.o



obj-$(CONFIG_CPU_HAS_PINT_IRQ)	+= pint.o

obj-$(CONFIG_CPU_HAS_INTC2_IRQ)	+= intc2.o

arch/sh/kernel/cpu/irq_imask.c→arch/sh/kernel/cpu/irq/imask.c

+5 −11
Original line number Diff line number Diff line 
/* $Id: irq_imask.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $

 *

 * linux/arch/sh/kernel/irq_imask.c

/*

 * arch/sh/kernel/cpu/irq/imask.c

 *

 * Copyright (C) 1999, 2000  Niibe Yutaka

 *

 * Simple interrupt handling using IMASK of SR register.

 *

 */



/* NOTE: Will not work on level 15 */





#include <linux/ptrace.h>

#include <linux/errno.h>

#include <linux/kernel_stat.h>
@@ -19,13 +15,11 @@ 
#include <linux/interrupt.h>

#include <linux/init.h>

#include <linux/bitops.h>



#include <asm/system.h>

#include <asm/irq.h>



#include <linux/spinlock.h>

#include <linux/cache.h>

#include <linux/irq.h>

#include <asm/system.h>

#include <asm/irq.h>



/* Bitmap of IRQ masked */

static unsigned long imask_mask = 0x7fff;

arch/sh/kernel/cpu/sh4/irq_intc2.c→arch/sh/kernel/cpu/irq/intc2.c

+284 −0
Original line number Diff line number Diff line 
/*

 * linux/arch/sh/kernel/irq_intc2.c

 * Interrupt handling for INTC2-based IRQ.

 *

 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)

 * Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)

 *

 * May be copied or modified under the terms of the GNU General Public

 * License.  See linux/COPYING for more information.

 *

 * Interrupt handling for INTC2-based IRQ.

 *

 * These are the "new Hitachi style" interrupts, as present on the

 * Hitachi 7751 and the STM ST40 STB1.

 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/irq.h>



#include <asm/system.h>

#include <asm/io.h>

#include <asm/machvec.h>





struct intc2_data {

	unsigned char msk_offset;

	unsigned char msk_shift;

#ifdef CONFIG_CPU_SUBTYPE_ST40



	int (*clear_irq) (int);

#endif

};





static struct intc2_data intc2_data[NR_INTC2_IRQS];



static void enable_intc2_irq(unsigned int irq);
@@ -62,8 +57,8 @@ static void disable_intc2_irq(unsigned int irq) 
	int irq_offset = irq - INTC2_FIRST_IRQ;

	int msk_shift, msk_offset;



	// Sanity check

	if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))

	/* Sanity check */

	if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))

		return;



	msk_shift = intc2_data[irq_offset].msk_shift;
@@ -79,7 +74,7 @@ static void enable_intc2_irq(unsigned int irq) 
	int msk_shift, msk_offset;



	/* Sanity check */

	if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))

	if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))

		return;



	msk_shift = intc2_data[irq_offset].msk_shift;
@@ -99,10 +94,8 @@ static void end_intc2_irq(unsigned int irq) 
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))

		enable_intc2_irq(irq);



#ifdef CONFIG_CPU_SUBTYPE_ST40

	if (intc2_data[irq - INTC2_FIRST_IRQ].clear_irq)

	if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq))

		intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq);

#endif

}



/*
@@ -124,7 +117,7 @@ void make_intc2_irq(unsigned int irq, 
	unsigned int flags;

	unsigned long ipr;



	if((irq_offset<0) || (irq_offset>=NR_INTC2_IRQS))

	if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))

		return;



	disable_irq_nosync(irq);
@@ -132,16 +125,14 @@ void make_intc2_irq(unsigned int irq, 
	/* Fill the data we need */

	intc2_data[irq_offset].msk_offset = msk_offset;

	intc2_data[irq_offset].msk_shift  = msk_shift;

#ifdef CONFIG_CPU_SUBTYPE_ST40

	intc2_data[irq_offset].clear_irq = NULL;

#endif



	/* Set the priority level */

	local_irq_save(flags);



	ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);

	ipr &= ~(0xf << ipr_shift);

	ipr|=(priority)<<ipr_shift;

	ipr |= priority << ipr_shift;

	ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);



	local_irq_restore(flags);
@@ -151,72 +142,143 @@ void make_intc2_irq(unsigned int irq, 
	disable_intc2_irq(irq);

}



#ifdef CONFIG_CPU_SUBTYPE_ST40



struct intc2_init {

static struct intc2_init {

	unsigned short irq;

	unsigned char ipr_offset, ipr_shift;

	unsigned char msk_offset, msk_shift;

};



static struct intc2_init intc2_init_data[]  __initdata = {

	{64,  0,  0, 0,  0},	/* PCI serr */

	{65,  0,  4, 0,  1},	/* PCI err */

	{66,  0,  4, 0,  2},	/* PCI ad */

	{67,  0,  4, 0,  3},	/* PCI pwd down */

	{72,  0,  8, 0,  5},	/* DMAC INT0 */

	{73,  0,  8, 0,  6},	/* DMAC INT1 */

	{74,  0,  8, 0,  7},	/* DMAC INT2 */

	{75,  0,  8, 0,  8},	/* DMAC INT3 */

	{76,  0,  8, 0,  9},	/* DMAC INT4 */

	{78,  0,  8, 0, 11},	/* DMAC ERR */

	{80,  0, 12, 0, 12},	/* PIO0 */

	{84,  0, 16, 0, 13},	/* PIO1 */

	{88,  0, 20, 0, 14},	/* PIO2 */

	{112, 4,  0, 4,  0},	/* Mailbox */

	unsigned char priority;

} intc2_init_data[]  __initdata = {

#if defined(CONFIG_CPU_SUBTYPE_ST40)

	{64,  0,  0, 0,  0, 13},	/* PCI serr */

	{65,  0,  4, 0,  1, 13},	/* PCI err */

	{66,  0,  4, 0,  2, 13},	/* PCI ad */

	{67,  0,  4, 0,  3, 13},	/* PCI pwd down */

	{72,  0,  8, 0,  5, 13},	/* DMAC INT0 */

	{73,  0,  8, 0,  6, 13},	/* DMAC INT1 */

	{74,  0,  8, 0,  7, 13},	/* DMAC INT2 */

	{75,  0,  8, 0,  8, 13},	/* DMAC INT3 */

	{76,  0,  8, 0,  9, 13},	/* DMAC INT4 */

	{78,  0,  8, 0, 11, 13},	/* DMAC ERR */

	{80,  0, 12, 0, 12, 13},	/* PIO0 */

	{84,  0, 16, 0, 13, 13},	/* PIO1 */

	{88,  0, 20, 0, 14, 13},	/* PIO2 */

	{112, 4,  0, 4,  0, 13},	/* Mailbox */

 #ifdef CONFIG_CPU_SUBTYPE_ST40GX1

	{116, 4,  4, 4,  4},	/* SSC0 */

	{120, 4,  8, 4,  8},	/* IR Blaster */

	{124, 4, 12, 4, 12},	/* USB host */

	{128, 4, 16, 4, 16},	/* Video processor BLITTER */

	{132, 4, 20, 4, 20},	/* UART0 */

	{134, 4, 20, 4, 22},	/* UART2 */

	{136, 4, 24, 4, 24},	/* IO_PIO0 */

	{140, 4, 28, 4, 28},	/* EMPI */

	{144, 8,  0, 8,  0},	/* MAFE */

	{148, 8,  4, 8,  4},	/* PWM */

	{152, 8,  8, 8,  8},	/* SSC1 */

	{156, 8, 12, 8, 12},	/* IO_PIO1 */

	{160, 8, 16, 8, 16},	/* USB target */

	{164, 8, 20, 8, 20},	/* UART1 */

	{168, 8, 24, 8, 24},	/* Teletext */

	{172, 8, 28, 8, 28},	/* VideoSync VTG */

	{173, 8, 28, 8, 29},	/* VideoSync DVP0 */

	{174, 8, 28, 8, 30},	/* VideoSync DVP1 */

	{116, 4,  4, 4,  4, 13},	/* SSC0 */

	{120, 4,  8, 4,  8, 13},	/* IR Blaster */

	{124, 4, 12, 4, 12, 13},	/* USB host */

	{128, 4, 16, 4, 16, 13},	/* Video processor BLITTER */

	{132, 4, 20, 4, 20, 13},	/* UART0 */

	{134, 4, 20, 4, 22, 13},	/* UART2 */

	{136, 4, 24, 4, 24, 13},	/* IO_PIO0 */

	{140, 4, 28, 4, 28, 13},	/* EMPI */

	{144, 8,  0, 8,  0, 13},	/* MAFE */

	{148, 8,  4, 8,  4, 13},	/* PWM */

	{152, 8,  8, 8,  8, 13},	/* SSC1 */

	{156, 8, 12, 8, 12, 13},	/* IO_PIO1 */

	{160, 8, 16, 8, 16, 13},	/* USB target */

	{164, 8, 20, 8, 20, 13},	/* UART1 */

	{168, 8, 24, 8, 24, 13},	/* Teletext */

	{172, 8, 28, 8, 28, 13},	/* VideoSync VTG */

	{173, 8, 28, 8, 29, 13},	/* VideoSync DVP0 */

	{174, 8, 28, 8, 30, 13},	/* VideoSync DVP1 */

#endif

#elif defined(CONFIG_CPU_SUBTYPE_SH7760)

/*

 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0

 */

	/* INTPRIO0 | INTMSK0 */

	{48,  0, 28, 0, 31,  3},	/* IRQ 4 */

	{49,  0, 24, 0, 30,  3},	/* IRQ 3 */

	{50,  0, 20, 0, 29,  3},	/* IRQ 2 */

	{51,  0, 16, 0, 28,  3},	/* IRQ 1 */

	/* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */

	/* INTPRIO4 | INTMSK0 */

	{56,  4, 28, 0, 25,  3},	/* HCAN2_CHAN0 */

	{57,  4, 24, 0, 24,  3},	/* HCAN2_CHAN1 */

	{58,  4, 20, 0, 23,  3},	/* I2S_CHAN0   */

	{59,  4, 16, 0, 22,  3},	/* I2S_CHAN1   */

	{60,  4, 12, 0, 21,  3},	/* AC97_CHAN0  */

	{61,  4,  8, 0, 20,  3},	/* AC97_CHAN1  */

	{62,  4,  4, 0, 19,  3},	/* I2C_CHAN0   */

	{63,  4,  0, 0, 18,  3},	/* I2C_CHAN1   */

	/* INTPRIO8 | INTMSK0 */

	{52,  8, 16, 0, 11,  3},	/* SCIF0_ERI_IRQ */

	{53,  8, 16, 0, 10,  3},	/* SCIF0_RXI_IRQ */

	{54,  8, 16, 0,  9,  3},	/* SCIF0_BRI_IRQ */

	{55,  8, 16, 0,  8,  3},	/* SCIF0_TXI_IRQ */

	{64,  8, 28, 0, 17,  3},	/* USBHI_IRQ */

	{65,  8, 24, 0, 16,  3},	/* LCDC      */

	/* 66, 67 unused */

	{68,  8, 20, 0, 14, 13},	/* DMABRGI0_IRQ */

	{69,  8, 20, 0, 13, 13},	/* DMABRGI1_IRQ */

	{70,  8, 20, 0, 12, 13},	/* DMABRGI2_IRQ */

	/* 71 unused */

	{72,  8, 12, 0,  7,  3},	/* SCIF1_ERI_IRQ */

	{73,  8, 12, 0,  6,  3},	/* SCIF1_RXI_IRQ */

	{74,  8, 12, 0,  5,  3},	/* SCIF1_BRI_IRQ */

	{75,  8, 12, 0,  4,  3},	/* SCIF1_TXI_IRQ */

	{76,  8,  8, 0,  3,  3},	/* SCIF2_ERI_IRQ */

	{77,  8,  8, 0,  2,  3},	/* SCIF2_RXI_IRQ */

	{78,  8,  8, 0,  1,  3},	/* SCIF2_BRI_IRQ */

	{79,  8,  8, 0,  0,  3},	/* SCIF2_TXI_IRQ */

	/*          | INTMSK4 */

	{80,  8,  4, 4, 23,  3},	/* SIM_ERI */

	{81,  8,  4, 4, 22,  3},	/* SIM_RXI */

	{82,  8,  4, 4, 21,  3},	/* SIM_TXI */

	{83,  8,  4, 4, 20,  3},	/* SIM_TEI */

	{84,  8,  0, 4, 19,  3},	/* HSPII */

	/* INTPRIOC | INTMSK4 */

	/* 85-87 unused/reserved */

	{88, 12, 20, 4, 18,  3},	/* MMCI0 */

	{89, 12, 20, 4, 17,  3},	/* MMCI1 */

	{90, 12, 20, 4, 16,  3},	/* MMCI2 */

	{91, 12, 20, 4, 15,  3},	/* MMCI3 */

	{92, 12, 12, 4,  6,  3},	/* MFI (unsure, bug? in my 7760 manual*/

	/* 93-107 reserved/undocumented */

	{108,12,  4, 4,  1,  3},	/* ADC  */

	{109,12,  0, 4,  0,  3},	/* CMTI */

	/* 110-111 reserved/unused */

#elif defined(CONFIG_CPU_SUBTYPE_SH7780)

	{ TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},

#ifdef CONFIG_SH_RTC

	{ RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },

#endif

	{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },

	{ SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },



	{ SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },

	{ SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },



	{ PCIC0_IRQ, 0x10,  8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },

	{ PCIC1_IRQ, 0x10,  0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },

	{ PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },

	{ PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },

	{ PCIC4_IRQ, 0x14,  8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },

#endif

};



void __init init_IRQ_intc2(void)

{

	struct intc2_init *p;



	printk(KERN_ALERT "init_IRQ_intc2\n");

	int i;



	for (p = intc2_init_data;

	     p<intc2_init_data+ARRAY_SIZE(intc2_init_data);

	     p++) {

	for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) {

		struct intc2_init *p = intc2_init_data + i;

		make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,

			       p-> msk_offset, p->msk_shift, 13);

			       p-> msk_offset, p->msk_shift, p->priority);

	}

}



/* Adds a termination callback to the interrupt */

void intc2_add_clear_irq(int irq, int (*fn)(int))

{

	if (irq < INTC2_FIRST_IRQ)

	if (unlikely(irq < INTC2_FIRST_IRQ))

		return;



	intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;

}

#endif /* CONFIG_CPU_SUBTYPE_ST40 */

arch/sh/kernel/cpu/irq_ipr.c→arch/sh/kernel/cpu/irq/ipr.c

+42 −175
Original line number Diff line number Diff line 
/* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $

 *

 * linux/arch/sh/kernel/irq_ipr.c

/*

 * arch/sh/kernel/cpu/irq/ipr.c

 *

 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi

 * Copyright (C) 2000  Kazumoto Kojima
@@ -109,7 +108,8 @@ static void end_ipr_irq(unsigned int irq) 
		enable_ipr_irq(irq);

}



void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)

void make_ipr_irq(unsigned int irq, unsigned int addr, int pos,

		  int priority, int maskpos)

{

	disable_irq_nosync(irq);

	ipr_data[irq].addr = addr;
@@ -120,126 +120,47 @@ void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 
	disable_ipr_irq(irq);

}



#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \

    defined(CONFIG_CPU_SUBTYPE_SH7707) || \

    defined(CONFIG_CPU_SUBTYPE_SH7709)

static unsigned char pint_map[256];

static unsigned long portcr_mask = 0;



static void enable_pint_irq(unsigned int irq);

static void disable_pint_irq(unsigned int irq);



/* shutdown is same as "disable" */

#define shutdown_pint_irq disable_pint_irq



static void mask_and_ack_pint(unsigned int);

static void end_pint_irq(unsigned int irq);



static unsigned int startup_pint_irq(unsigned int irq)

{

	enable_pint_irq(irq);

	return 0; /* never anything pending */

}



static struct hw_interrupt_type pint_irq_type = {

	.typename = "PINT-IRQ",

	.startup = startup_pint_irq,

	.shutdown = shutdown_pint_irq,

	.enable = enable_pint_irq,

	.disable = disable_pint_irq,

	.ack = mask_and_ack_pint,

	.end = end_pint_irq

};



static void disable_pint_irq(unsigned int irq)

{

	unsigned long val, flags;



	local_irq_save(flags);

	val = ctrl_inw(INTC_INTER);

	val &= ~(1 << (irq - PINT_IRQ_BASE));

	ctrl_outw(val, INTC_INTER);	/* disable PINTn */

	portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);

	local_irq_restore(flags);

}



static void enable_pint_irq(unsigned int irq)

{

	unsigned long val, flags;



	local_irq_save(flags);

	val = ctrl_inw(INTC_INTER);

	val |= 1 << (irq - PINT_IRQ_BASE);

	ctrl_outw(val, INTC_INTER);	/* enable PINTn */

	portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;

	local_irq_restore(flags);

}



static void mask_and_ack_pint(unsigned int irq)

{

	disable_pint_irq(irq);

}



static void end_pint_irq(unsigned int irq)

{

	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))

		enable_pint_irq(irq);

}



void make_pint_irq(unsigned int irq)

{

	disable_irq_nosync(irq);

	irq_desc[irq].handler = &pint_irq_type;

	disable_pint_irq(irq);

}

#endif



void __init init_IRQ(void)

{

#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \

    defined(CONFIG_CPU_SUBTYPE_SH7707) || \

    defined(CONFIG_CPU_SUBTYPE_SH7709)

	int i;

#endif



	make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);

	make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);

#ifndef CONFIG_CPU_SUBTYPE_SH7780

	make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY, 0);

	make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY, 0);

#if defined(CONFIG_SH_RTC)

	make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);

	make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY, 0);

#endif



#ifdef SCI_ERI_IRQ

	make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);

	make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);

	make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);

	make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);

	make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);

	make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY, 0);

#endif



#ifdef SCIF1_ERI_IRQ

	make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);

	make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);

	make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);

	make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);

	make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);

	make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);

	make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);

	make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY, 0);

#endif



#if defined(CONFIG_CPU_SUBTYPE_SH7300)

	make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);

	make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);

	make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);

	make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);

	make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY, 0);

	make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0);

	make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY, 0);

	make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY, 0);

#endif



#ifdef SCIF_ERI_IRQ

	make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);

	make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);

	make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);

	make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);

	make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);

	make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);

	make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);

	make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY, 0);

#endif



#ifdef IRDA_ERI_IRQ

	make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);

	make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);

	make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);

	make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);

	make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);

	make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);

	make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);

	make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY, 0);

#endif



#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
@@ -254,86 +175,32 @@ void __init init_IRQ(void) 
	 * You should set corresponding bits of PFC to "00"

	 * to enable these interrupts.

	 */

	make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);

	make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);

	make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);

	make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);

	make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);

	make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);

#if !defined(CONFIG_CPU_SUBTYPE_SH7300)

	make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);

	make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);

	enable_ipr_irq(PINT0_IRQ);

	enable_ipr_irq(PINT8_IRQ);

	make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY, 0);

	make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY, 0);

	make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY, 0);

	make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY, 0);

	make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY, 0);

	make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY, 0);

#endif

#endif



	for(i = 0; i < 16; i++)

		make_pint_irq(PINT_IRQ_BASE + i);

	for(i = 0; i < 256; i++)

	{

		if(i & 1) pint_map[i] = 0;

		else if(i & 2) pint_map[i] = 1;

		else if(i & 4) pint_map[i] = 2;

		else if(i & 8) pint_map[i] = 3;

		else if(i & 0x10) pint_map[i] = 4;

		else if(i & 0x20) pint_map[i] = 5;

		else if(i & 0x40) pint_map[i] = 6;

		else if(i & 0x80) pint_map[i] = 7;

	}

#endif /* !CONFIG_CPU_SUBTYPE_SH7300 */

#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709  || CONFIG_CPU_SUBTYPE_SH7300*/

#ifdef CONFIG_CPU_HAS_PINT_IRQ

	init_IRQ_pint();

#endif



#ifdef CONFIG_CPU_SUBTYPE_ST40

#ifdef CONFIG_CPU_HAS_INTC2_IRQ

	init_IRQ_intc2();

#endif



	/* Perform the machine specific initialisation */

	if (sh_mv.mv_init_irq != NULL) {

	if (sh_mv.mv_init_irq != NULL)

		sh_mv.mv_init_irq();

}

}

#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \

    defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)

int ipr_irq_demux(int irq)

{

#if !defined(CONFIG_CPU_SUBTYPE_SH7300)

	unsigned long creg, dreg, d, sav;



	if(irq == PINT0_IRQ)

	{

#if defined(CONFIG_CPU_SUBTYPE_SH7707)

		creg = PORT_PACR;

		dreg = PORT_PADR;

#else

		creg = PORT_PCCR;

		dreg = PORT_PCDR;

#endif

		sav = ctrl_inw(creg);

		ctrl_outw(sav | portcr_mask, creg);

		d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;

		ctrl_outw(sav, creg);

		if(d == 0) return irq;

		return PINT_IRQ_BASE + pint_map[d];

	}

	else if(irq == PINT8_IRQ)

#if !defined(CONFIG_CPU_HAS_PINT_IRQ)

int ipr_irq_demux(int irq)

{

#if defined(CONFIG_CPU_SUBTYPE_SH7707)

		creg = PORT_PBCR;

		dreg = PORT_PBDR;

#else

		creg = PORT_PFCR;

		dreg = PORT_PFDR;

#endif

		sav = ctrl_inw(creg);

		ctrl_outw(sav | (portcr_mask >> 16), creg);

		d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;

		ctrl_outw(sav, creg);

		if(d == 0) return irq;

		return PINT_IRQ_BASE + 8 + pint_map[d];

	}

#endif

	return irq;

}

#endif



EXPORT_SYMBOL(make_ipr_irq);