Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit bda65b42 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'mlx5-4kuar-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux 



Saeed Mahameed says:

====================
mlx5 4K UAR

The following series of patches optimizes the usage of the UAR area which is
contained within the BAR 0-1. Previous versions of the firmware and the driver
assumed each system page contains a single UAR. This patch set will query the
firmware for a new capability that if published, means that the firmware can
support UARs of fixed 4K regardless of system page size. In the case of
powerpc, where page size equals 64KB, this means we can utilize 16 UARs per
system page. Since user space processes by default consume eight UARs per
context this means that with this change a process will need a single system
page to fulfill that requirement and in fact make use of more UARs which is
better in terms of performance.

In addition to optimizing user-space processes, we introduce an allocator
that can be used by kernel consumers to allocate blue flame registers
(which are areas within a UAR that are used to write doorbells). This provides
further optimization on using the UAR area since the Ethernet driver makes
use of a single blue flame register per system page and now it will use two
blue flame registers per 4K.

The series also makes changes to naming conventions and now the terms used in
the driver code match the terms used in the PRM (programmers reference manual).
Thus, what used to be called UUAR (micro UAR) is now called BFREG (blue flame
register).

In order to support compatibility between different versions of
library/driver/firmware, the library has now means to notify the kernel driver
that it supports the new scheme and the kernel can notify the library if it
supports this extension. So mixed versions of libraries can run concurrently
without any issues.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b369e7fd f502d834

drivers/infiniband/hw/mlx5/cq.c

+4 −6
Original line number Diff line number Diff line
@@ -689,7 +689,7 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 
{

	struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;

	struct mlx5_ib_cq *cq = to_mcq(ibcq);

	void __iomem *uar_page = mdev->priv.uuari.uars[0].map;

	void __iomem *uar_page = mdev->priv.uar->map;

	unsigned long irq_flags;

	int ret = 0;
@@ -704,9 +704,7 @@ int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 
	mlx5_cq_arm(&cq->mcq,

		    (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?

		    MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,

		    uar_page,

		    MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock),

		    to_mcq(ibcq)->mcq.cons_index);

		    uar_page, to_mcq(ibcq)->mcq.cons_index);



	return ret;

}
@@ -790,7 +788,7 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 
	MLX5_SET(cqc, cqc, log_page_size,

		 page_shift - MLX5_ADAPTER_PAGE_SHIFT);



	*index = to_mucontext(context)->uuari.uars[0].index;

	*index = to_mucontext(context)->bfregi.sys_pages[0];



	if (ucmd.cqe_comp_en == 1) {

		if (unlikely((*cqe_size != 64) ||
@@ -886,7 +884,7 @@ static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 
	MLX5_SET(cqc, cqc, log_page_size,

		 cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);



	*index = dev->mdev->priv.uuari.uars[0].index;

	*index = dev->mdev->priv.uar->index;



	return 0;

drivers/infiniband/hw/mlx5/main.c

+185 −93
Original line number Diff line number Diff line
@@ -992,6 +992,86 @@ static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 
	return err;

}



static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)

{

	mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",

		    caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");

}



static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,

			     struct mlx5_ib_alloc_ucontext_req_v2 *req,

			     u32 *num_sys_pages)

{

	int uars_per_sys_page;

	int bfregs_per_sys_page;

	int ref_bfregs = req->total_num_bfregs;



	if (req->total_num_bfregs == 0)

		return -EINVAL;



	BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);

	BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);



	if (req->total_num_bfregs > MLX5_MAX_BFREGS)

		return -ENOMEM;



	uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);

	bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;

	req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);

	*num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;



	if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)

		return -EINVAL;



	mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",

		    MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",

		    lib_uar_4k ? "yes" : "no", ref_bfregs,

		    req->total_num_bfregs, *num_sys_pages);



	return 0;

}



static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)

{

	struct mlx5_bfreg_info *bfregi;

	int err;

	int i;



	bfregi = &context->bfregi;

	for (i = 0; i < bfregi->num_sys_pages; i++) {

		err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);

		if (err)

			goto error;



		mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);

	}

	return 0;



error:

	for (--i; i >= 0; i--)

		if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))

			mlx5_ib_warn(dev, "failed to free uar %d\n", i);



	return err;

}



static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)

{

	struct mlx5_bfreg_info *bfregi;

	int err;

	int i;



	bfregi = &context->bfregi;

	for (i = 0; i < bfregi->num_sys_pages; i++) {

		err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);

		if (err) {

			mlx5_ib_warn(dev, "failed to free uar %d\n", i);

			return err;

		}

	}

	return 0;

}



static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,

						  struct ib_udata *udata)

{
@@ -999,17 +1079,13 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	struct mlx5_ib_alloc_ucontext_req_v2 req = {};

	struct mlx5_ib_alloc_ucontext_resp resp = {};

	struct mlx5_ib_ucontext *context;

	struct mlx5_uuar_info *uuari;

	struct mlx5_uar *uars;

	int gross_uuars;

	int num_uars;

	struct mlx5_bfreg_info *bfregi;

	int ver;

	int uuarn;

	int err;

	int i;

	size_t reqlen;

	size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,

				     max_cqe_version);

	bool lib_uar_4k;



	if (!dev->ib_active)

		return ERR_PTR(-EAGAIN);
@@ -1032,27 +1108,14 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	if (req.flags)

		return ERR_PTR(-EINVAL);



	if (req.total_num_uuars > MLX5_MAX_UUARS)

		return ERR_PTR(-ENOMEM);



	if (req.total_num_uuars == 0)

		return ERR_PTR(-EINVAL);



	if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)

		return ERR_PTR(-EOPNOTSUPP);



	if (reqlen > sizeof(req) &&

	    !ib_is_udata_cleared(udata, sizeof(req),

				 reqlen - sizeof(req)))

		return ERR_PTR(-EOPNOTSUPP);



	req.total_num_uuars = ALIGN(req.total_num_uuars,

				    MLX5_NON_FP_BF_REGS_PER_PAGE);

	if (req.num_low_latency_uuars > req.total_num_uuars - 1)

	req.total_num_bfregs = ALIGN(req.total_num_bfregs,

				    MLX5_NON_FP_BFREGS_PER_UAR);

	if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)

		return ERR_PTR(-EINVAL);



	num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;

	gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;

	resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);

	if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))

		resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
@@ -1065,6 +1128,10 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	resp.cqe_version = min_t(__u8,

				 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),

				 req.max_cqe_version);

	resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?

				MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;

	resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?

					MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;

	resp.response_length = min(offsetof(typeof(resp), response_length) +

				   sizeof(resp.response_length), udata->outlen);
@@ -1072,41 +1139,34 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	if (!context)

		return ERR_PTR(-ENOMEM);



	uuari = &context->uuari;

	mutex_init(&uuari->lock);

	uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);

	if (!uars) {

		err = -ENOMEM;

	lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;

	bfregi = &context->bfregi;



	/* updates req->total_num_bfregs */

	err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);

	if (err)

		goto out_ctx;

	}



	uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),

				sizeof(*uuari->bitmap),

	mutex_init(&bfregi->lock);

	bfregi->lib_uar_4k = lib_uar_4k;

	bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),

				GFP_KERNEL);

	if (!uuari->bitmap) {

	if (!bfregi->count) {

		err = -ENOMEM;

		goto out_uar_ctx;

	}

	/*

	 * clear all fast path uuars

	 */

	for (i = 0; i < gross_uuars; i++) {

		uuarn = i & 3;

		if (uuarn == 2 || uuarn == 3)

			set_bit(i, uuari->bitmap);

		goto out_ctx;

	}



	uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);

	if (!uuari->count) {

	bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,

				    sizeof(*bfregi->sys_pages),

				    GFP_KERNEL);

	if (!bfregi->sys_pages) {

		err = -ENOMEM;

		goto out_bitmap;

		goto out_count;

	}



	for (i = 0; i < num_uars; i++) {

		err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);

	err = allocate_uars(dev, context);

	if (err)

			goto out_count;

	}

		goto out_sys_pages;



#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING

	context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
@@ -1130,7 +1190,7 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	INIT_LIST_HEAD(&context->db_page_list);

	mutex_init(&context->db_page_mutex);



	resp.tot_uuars = req.total_num_uuars;

	resp.tot_bfregs = req.total_num_bfregs;

	resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);



	if (field_avail(typeof(resp), cqe_version, udata->outlen))
@@ -1148,26 +1208,32 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	 * pretend we don't support reading the HCA's core clock. This is also

	 * forced by mmap function.

	 */

	if (PAGE_SIZE <= 4096 &&

	    field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {

	if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {

		if (PAGE_SIZE <= 4096) {

			resp.comp_mask |=

				MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;

			resp.hca_core_clock_offset =

			offsetof(struct mlx5_init_seg, internal_timer_h) %

			PAGE_SIZE;

				offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;

		}

		resp.response_length += sizeof(resp.hca_core_clock_offset) +

					sizeof(resp.reserved2);

	}



	if (field_avail(typeof(resp), log_uar_size, udata->outlen))

		resp.response_length += sizeof(resp.log_uar_size);



	if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))

		resp.response_length += sizeof(resp.num_uars_per_page);



	err = ib_copy_to_udata(udata, &resp, resp.response_length);

	if (err)

		goto out_td;



	uuari->ver = ver;

	uuari->num_low_latency_uuars = req.num_low_latency_uuars;

	uuari->uars = uars;

	uuari->num_uars = num_uars;

	bfregi->ver = ver;

	bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;

	context->cqe_version = resp.cqe_version;

	context->lib_caps = req.lib_caps;

	print_lib_caps(dev, context->lib_caps);



	return &context->ibucontext;
@@ -1179,19 +1245,17 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 
	free_page(context->upd_xlt_page);



out_uars:

	for (i--; i >= 0; i--)

		mlx5_cmd_free_uar(dev->mdev, uars[i].index);

out_count:

	kfree(uuari->count);

	deallocate_uars(dev, context);



out_bitmap:

	kfree(uuari->bitmap);

out_sys_pages:

	kfree(bfregi->sys_pages);



out_uar_ctx:

	kfree(uars);

out_count:

	kfree(bfregi->count);



out_ctx:

	kfree(context);



	return ERR_PTR(err);

}
@@ -1199,30 +1263,31 @@ static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 
{

	struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);

	struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);

	struct mlx5_uuar_info *uuari = &context->uuari;

	int i;

	struct mlx5_bfreg_info *bfregi;



	bfregi = &context->bfregi;

	if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))

		mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);



	free_page(context->upd_xlt_page);



	for (i = 0; i < uuari->num_uars; i++) {

		if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))

			mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);

	}



	kfree(uuari->count);

	kfree(uuari->bitmap);

	kfree(uuari->uars);

	deallocate_uars(dev, context);

	kfree(bfregi->sys_pages);

	kfree(bfregi->count);

	kfree(context);



	return 0;

}



static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)

static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,

				 struct mlx5_bfreg_info *bfregi,

				 int idx)

{

	return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;

	int fw_uars_per_page;



	fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;



	return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +

			bfregi->sys_pages[idx] / fw_uars_per_page;

}



static int get_command(unsigned long offset)
@@ -1377,11 +1442,23 @@ static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 
		    struct vm_area_struct *vma,

		    struct mlx5_ib_ucontext *context)

{

	struct mlx5_uuar_info *uuari = &context->uuari;

	struct mlx5_bfreg_info *bfregi = &context->bfregi;

	int err;

	unsigned long idx;

	phys_addr_t pfn, pa;

	pgprot_t prot;

	int uars_per_page;



	if (vma->vm_end - vma->vm_start != PAGE_SIZE)

		return -EINVAL;



	uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);

	idx = get_index(vma->vm_pgoff);

	if (idx % uars_per_page ||

	    idx * uars_per_page >= bfregi->num_sys_pages) {

		mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);

		return -EINVAL;

	}



	switch (cmd) {

	case MLX5_IB_MMAP_WC_PAGE:
@@ -1404,14 +1481,7 @@ static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 
		return -EINVAL;

	}



	if (vma->vm_end - vma->vm_start != PAGE_SIZE)

		return -EINVAL;



	idx = get_index(vma->vm_pgoff);

	if (idx >= uuari->num_uars)

		return -EINVAL;



	pfn = uar_index2pfn(dev, uuari->uars[idx].index);

	pfn = uar_index2pfn(dev, bfregi, idx);

	mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);



	vma->vm_page_prot = prot;
@@ -3072,8 +3142,6 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 
	if (mlx5_use_mad_ifc(dev))

		get_ext_port_caps(dev);



	MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);



	if (!mlx5_lag_is_active(mdev))

		name = "mlx5_%d";

	else
@@ -3249,9 +3317,21 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 
	if (err)

		goto err_odp;



	dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);

	if (!dev->mdev->priv.uar)

		goto err_q_cnt;



	err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);

	if (err)

		goto err_uar_page;



	err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);

	if (err)

		goto err_bfreg;



	err = ib_register_device(&dev->ib_dev, NULL);

	if (err)

		goto err_q_cnt;

		goto err_fp_bfreg;



	err = create_umr_res(dev);

	if (err)
@@ -3274,6 +3354,15 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 
err_dev:

	ib_unregister_device(&dev->ib_dev);



err_fp_bfreg:

	mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);



err_bfreg:

	mlx5_free_bfreg(dev->mdev, &dev->bfreg);



err_uar_page:

	mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);



err_q_cnt:

	mlx5_ib_dealloc_q_counters(dev);
@@ -3305,6 +3394,9 @@ static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 


	mlx5_remove_netdev_notifier(dev);

	ib_unregister_device(&dev->ib_dev);

	mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);

	mlx5_free_bfreg(dev->mdev, &dev->bfreg);

	mlx5_put_uars_page(dev->mdev, mdev->priv.uar);

	mlx5_ib_dealloc_q_counters(dev);

	destroy_umrc_res(dev);

	mlx5_ib_odp_remove_one(dev);

drivers/infiniband/hw/mlx5/mlx5_ib.h

+26 −6
Original line number Diff line number Diff line
@@ -90,7 +90,6 @@ enum mlx5_ib_latency_class { 
	MLX5_IB_LATENCY_CLASS_LOW,

	MLX5_IB_LATENCY_CLASS_MEDIUM,

	MLX5_IB_LATENCY_CLASS_HIGH,

	MLX5_IB_LATENCY_CLASS_FAST_PATH

};



enum mlx5_ib_mad_ifc_flags {
@@ -100,7 +99,7 @@ enum mlx5_ib_mad_ifc_flags { 
};



enum {

	MLX5_CROSS_CHANNEL_UUAR         = 0,

	MLX5_CROSS_CHANNEL_BFREG         = 0,

};



enum {
@@ -120,7 +119,7 @@ struct mlx5_ib_ucontext { 
	/* protect doorbell record alloc/free

	 */

	struct mutex		db_page_mutex;

	struct mlx5_uuar_info	uuari;

	struct mlx5_bfreg_info	bfregi;

	u8			cqe_version;

	/* Transport Domain number */

	u32			tdn;
@@ -129,6 +128,7 @@ struct mlx5_ib_ucontext { 
	unsigned long		upd_xlt_page;

	/* protect ODP/KSM */

	struct mutex		upd_xlt_page_mutex;

	u64			lib_caps;

};



static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
@@ -324,6 +324,12 @@ struct mlx5_ib_raw_packet_qp { 
	struct mlx5_ib_rq rq;

};



struct mlx5_bf {

	int			buf_size;

	unsigned long		offset;

	struct mlx5_sq_bfreg   *bfreg;

};



struct mlx5_ib_qp {

	struct ib_qp		ibqp;

	union {
@@ -349,13 +355,13 @@ struct mlx5_ib_qp { 
	int			wq_sig;

	int			scat_cqe;

	int			max_inline_data;

	struct mlx5_bf	       *bf;

	struct mlx5_bf	        bf;

	int			has_rq;



	/* only for user space QPs. For kernel

	 * we have it from the bf object

	 */

	int			uuarn;

	int			bfregn;



	int			create_type;
@@ -591,7 +597,6 @@ struct mlx5_ib_dev { 
	struct ib_device		ib_dev;

	struct mlx5_core_dev		*mdev;

	struct mlx5_roce		roce;

	MLX5_DECLARE_DOORBELL_LOCK(uar_lock);

	int				num_ports;

	/* serialize update of capability mask

	 */
@@ -621,6 +626,8 @@ struct mlx5_ib_dev { 
	struct list_head	qp_list;

	/* Array with num_ports elements */

	struct mlx5_ib_port	*port;

	struct mlx5_sq_bfreg     bfreg;

	struct mlx5_sq_bfreg     fp_bfreg;

};



static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
@@ -968,4 +975,17 @@ static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 


	return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);

}



static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)

{

	return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?

				MLX5_UARS_IN_PAGE : 1;

}



static inline int get_num_uars(struct mlx5_ib_dev *dev,

			       struct mlx5_bfreg_info *bfregi)

{

	return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_sys_pages;

}



#endif /* MLX5_IB_H */

drivers/infiniband/hw/mlx5/qp.c

+115 −175

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/mellanox/mlx5/core/cq.c

+2 −0
Original line number Diff line number Diff line
@@ -179,6 +179,8 @@ int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 
		mlx5_core_dbg(dev, "failed adding CP 0x%x to debug file system\n",

			      cq->cqn);



	cq->uar = dev->priv.uar;



	return 0;



err_cmd: