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Commit bd2bb1b9 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: add POWER_DOMAIN_PLLS 

And get/put it when needed. The special thing about this commit is
that it will now return false in ibx_pch_dpll_get_hw_state() in case
the power domain is not enabled. This will fix some WARNs we have when
we run pm_rpm on SNB.

Testcase: igt/pm_rpm
Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463


Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 96f6128c

drivers/gpu/drm/i915/i915_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -2043,6 +2043,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain) 
		return "VGA";

	case POWER_DOMAIN_AUDIO:

		return "AUDIO";

	case POWER_DOMAIN_PLLS:

		return "PLLS";

	case POWER_DOMAIN_INIT:

		return "INIT";

	default:

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -129,6 +129,7 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PORT_OTHER,

	POWER_DOMAIN_VGA,

	POWER_DOMAIN_AUDIO,

	POWER_DOMAIN_PLLS,

	POWER_DOMAIN_INIT,



	POWER_DOMAIN_NUM,

drivers/gpu/drm/i915/intel_display.c

+10 −0
Original line number Diff line number Diff line
@@ -1814,6 +1814,8 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc) 
	}

	WARN_ON(pll->on);



	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);



	DRM_DEBUG_KMS("enabling %s\n", pll->name);

	pll->enable(dev_priv, pll);

	pll->on = true;
@@ -1850,6 +1852,8 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc) 
	DRM_DEBUG_KMS("disabling %s\n", pll->name);

	pll->disable(dev_priv, pll);

	pll->on = false;



	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);

}



static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
@@ -11302,6 +11306,9 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 
{

	uint32_t val;



	if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))

		return false;



	val = I915_READ(PCH_DPLL(pll->id));

	hw_state->dpll = val;

	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
@@ -12867,6 +12874,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) 


		DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",

			      pll->name, pll->refcount, pll->on);



		if (pll->refcount)

			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);

	}



	list_for_each_entry(encoder, &dev->mode_config.encoder_list,

drivers/gpu/drm/i915/intel_pm.c

+1 −0
Original line number Diff line number Diff line
@@ -6346,6 +6346,7 @@ EXPORT_SYMBOL_GPL(i915_get_cdclk_freq); 
	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |		\

	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |		\

	BIT(POWER_DOMAIN_PORT_CRT) |			\

	BIT(POWER_DOMAIN_PLLS) |			\

	BIT(POWER_DOMAIN_INIT))

#define HSW_DISPLAY_POWER_DOMAINS (				\

	(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |	\