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Commit bbb8d343 authored by Harvey Harrison's avatar Harvey Harrison Committed by Linus Torvalds
Browse files

alpha: remove remaining __FUNCTION__ occurrences 



__FUNCTION__ is gcc-specific, use __func__

The change in pci-iommu,c should be safe as arena has not been assigned
when we get to this point.

Some were within #if 0 blocks, have changed them and left the blocks
as they appear to be debugging infrastructure.

A #define FN __FUNCTION__ was removed and occurances of FN were replaced
with __func__ as well.

Signed-off-by: default avatarHarvey Harrison <harvey.harrison@gmail.com>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent b901d40c

arch/alpha/kernel/core_marvel.c

+3 −3
Original line number Diff line number Diff line
@@ -994,7 +994,7 @@ marvel_agp_configure(alpha_agp_info *agp) 
		 * rate, but warn the user.

		 */

		printk("%s: unknown PLL setting RNGB=%lx (PLL6_CTL=%016lx)\n",

		       __FUNCTION__, IO7_PLL_RNGB(agp_pll), agp_pll);

		       __func__, IO7_PLL_RNGB(agp_pll), agp_pll);

		break;

	}
@@ -1044,13 +1044,13 @@ marvel_agp_translate(alpha_agp_info *agp, dma_addr_t addr) 


	if (addr < agp->aperture.bus_base ||

	    addr >= agp->aperture.bus_base + agp->aperture.size) {

		printk("%s: addr out of range\n", __FUNCTION__);

		printk("%s: addr out of range\n", __func__);

		return -EINVAL;

	}



	pte = aper->arena->ptes[baddr >> PAGE_SHIFT];

	if (!(pte & 1)) {

		printk("%s: pte not valid\n", __FUNCTION__);

		printk("%s: pte not valid\n", __func__);

		return -EINVAL;

	} 

	return (pte >> 1) << PAGE_SHIFT;

arch/alpha/kernel/core_t2.c

+9 −15
Original line number Diff line number Diff line
@@ -336,10 +336,7 @@ t2_direct_map_window1(unsigned long base, unsigned long length) 


#if DEBUG_PRINT_FINAL_SETTINGS

	printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",

	       __FUNCTION__,

	       *(vulp)T2_WBASE1,

	       *(vulp)T2_WMASK1,

	       *(vulp)T2_TBASE1);

	       __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);

#endif

}
@@ -366,10 +363,7 @@ t2_sg_map_window2(struct pci_controller *hose, 


#if DEBUG_PRINT_FINAL_SETTINGS

	printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",

	       __FUNCTION__,

	       *(vulp)T2_WBASE2,

	       *(vulp)T2_WMASK2,

	       *(vulp)T2_TBASE2);

	       __func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);

#endif

}
@@ -377,15 +371,15 @@ static void __init 
t2_save_configuration(void)

{

#if DEBUG_PRINT_INITIAL_SETTINGS

	printk("%s: HAE_1 was 0x%lx\n", __FUNCTION__, srm_hae); /* HW is 0 */

	printk("%s: HAE_2 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_2);

	printk("%s: HAE_3 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_3);

	printk("%s: HAE_4 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_4);

	printk("%s: HBASE was 0x%lx\n", __FUNCTION__, *(vulp)T2_HBASE);

	printk("%s: HAE_1 was 0x%lx\n", __func__, srm_hae); /* HW is 0 */

	printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2);

	printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3);

	printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4);

	printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE);



	printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __FUNCTION__, 

	printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __func__,

	       *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);

	printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __FUNCTION__, 

	printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __func__,

	       *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);

#endif

arch/alpha/kernel/core_titan.c

+17 −17
Original line number Diff line number Diff line
@@ -365,21 +365,21 @@ void __init 
titan_init_arch(void)

{

#if 0

	printk("%s: titan_init_arch()\n", __FUNCTION__);

	printk("%s: CChip registers:\n", __FUNCTION__);

	printk("%s: CSR_CSC 0x%lx\n", __FUNCTION__, TITAN_cchip->csc.csr);

	printk("%s: CSR_MTR 0x%lx\n", __FUNCTION__, TITAN_cchip->mtr.csr);

	printk("%s: CSR_MISC 0x%lx\n", __FUNCTION__, TITAN_cchip->misc.csr);

	printk("%s: CSR_DIM0 0x%lx\n", __FUNCTION__, TITAN_cchip->dim0.csr);

	printk("%s: CSR_DIM1 0x%lx\n", __FUNCTION__, TITAN_cchip->dim1.csr);

	printk("%s: CSR_DIR0 0x%lx\n", __FUNCTION__, TITAN_cchip->dir0.csr);

	printk("%s: CSR_DIR1 0x%lx\n", __FUNCTION__, TITAN_cchip->dir1.csr);

	printk("%s: CSR_DRIR 0x%lx\n", __FUNCTION__, TITAN_cchip->drir.csr);



	printk("%s: DChip registers:\n", __FUNCTION__);

	printk("%s: CSR_DSC 0x%lx\n", __FUNCTION__, TITAN_dchip->dsc.csr);

	printk("%s: CSR_STR 0x%lx\n", __FUNCTION__, TITAN_dchip->str.csr);

	printk("%s: CSR_DREV 0x%lx\n", __FUNCTION__, TITAN_dchip->drev.csr);

	printk("%s: titan_init_arch()\n", __func__);

	printk("%s: CChip registers:\n", __func__);

	printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr);

	printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr);

	printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr);

	printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);

	printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);

	printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);

	printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr);

	printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr);



	printk("%s: DChip registers:\n", __func__);

	printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);

	printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr);

	printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr);

#endif



	boot_cpuid = __hard_smp_processor_id();
@@ -700,13 +700,13 @@ titan_agp_translate(alpha_agp_info *agp, dma_addr_t addr) 


	if (addr < agp->aperture.bus_base ||

	    addr >= agp->aperture.bus_base + agp->aperture.size) {

		printk("%s: addr out of range\n", __FUNCTION__);

		printk("%s: addr out of range\n", __func__);

		return -EINVAL;

	}



	pte = aper->arena->ptes[baddr >> PAGE_SHIFT];

	if (!(pte & 1)) {

		printk("%s: pte not valid\n", __FUNCTION__);

		printk("%s: pte not valid\n", __func__);

		return -EINVAL;

	}

arch/alpha/kernel/core_tsunami.c

+13 −15
Original line number Diff line number Diff line
@@ -241,8 +241,6 @@ tsunami_probe_write(volatile unsigned long *vaddr) 
#define tsunami_probe_read(ADDR) 1

#endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */



#define FN __FUNCTION__



static void __init

tsunami_init_one_pchip(tsunami_pchip *pchip, int index)

{
@@ -383,27 +381,27 @@ tsunami_init_arch(void) 
	/* NXMs just don't matter to Tsunami--unless they make it

	   choke completely. */

	tmp = (unsigned long)(TSUNAMI_cchip - 1);

	printk("%s: probing bogus address:  0x%016lx\n", FN, bogus_addr);

	printk("%s: probing bogus address:  0x%016lx\n", __func__, bogus_addr);

	printk("\tprobe %s\n",

	       tsunami_probe_write((unsigned long *)bogus_addr)

	       ? "succeeded" : "failed");

#endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */



#if 0

	printk("%s: CChip registers:\n", FN);

	printk("%s: CSR_CSC 0x%lx\n", FN, TSUNAMI_cchip->csc.csr);

	printk("%s: CSR_MTR 0x%lx\n", FN, TSUNAMI_cchip.mtr.csr);

	printk("%s: CSR_MISC 0x%lx\n", FN, TSUNAMI_cchip->misc.csr);

	printk("%s: CSR_DIM0 0x%lx\n", FN, TSUNAMI_cchip->dim0.csr);

	printk("%s: CSR_DIM1 0x%lx\n", FN, TSUNAMI_cchip->dim1.csr);

	printk("%s: CSR_DIR0 0x%lx\n", FN, TSUNAMI_cchip->dir0.csr);

	printk("%s: CSR_DIR1 0x%lx\n", FN, TSUNAMI_cchip->dir1.csr);

	printk("%s: CSR_DRIR 0x%lx\n", FN, TSUNAMI_cchip->drir.csr);

	printk("%s: CChip registers:\n", __func__);

	printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);

	printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);

	printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);

	printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);

	printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);

	printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);

	printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);

	printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);



	printk("%s: DChip registers:\n");

	printk("%s: CSR_DSC 0x%lx\n", FN, TSUNAMI_dchip->dsc.csr);

	printk("%s: CSR_STR 0x%lx\n", FN, TSUNAMI_dchip->str.csr);

	printk("%s: CSR_DREV 0x%lx\n", FN, TSUNAMI_dchip->drev.csr);

	printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);

	printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);

	printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);

#endif

	/* With multiple PCI busses, we play with I/O as physical addrs.  */

	ioport_resource.end = ~0UL;

arch/alpha/kernel/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ pdev_save_srm_config(struct pci_dev *dev) 


	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);

	if (!tmp) {

		printk(KERN_ERR "%s: kmalloc() failed!\n", __FUNCTION__);

		printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);

		return;

	}

	tmp->next = srm_saved_configs;