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Commit bb428a5c authored Oct 09, 2017 by Tariq Toukan Committed by David S. Miller Oct 09, 2017

net/mlx4: Fix endianness issue in qp context params



Should take care of the endianness before assigning to params2 field.

Fixes: 53f33ae2 ("net/mlx4_core: Port aggregation upper layer interface")
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent acb40d84

drivers/net/ethernet/mellanox/mlx4/en_resources.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -53,7 +53,7 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
		if (is_tx) {
		context->sq_size_stride = ilog2(size) << 3 \| (ilog2(stride) - 4);
		if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)
		context->params2 \|= MLX4_QP_BIT_FPP;
		context->params2 \|= cpu_to_be32(MLX4_QP_BIT_FPP);

		} else {
		context->sq_size_stride = ilog2(TXBB_SIZE) - 4;

drivers/net/ethernet/mellanox/mlx4/qp.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -925,7 +925,7 @@ int mlx4_qp_to_ready(struct mlx4_dev dev, struct mlx4_mtt mtt,
		context->flags &= cpu_to_be32(~(0xf << 28));
		context->flags \|= cpu_to_be32(states[i + 1] << 28);
		if (states[i + 1] != MLX4_QP_STATE_RTR)
		context->params2 &= ~MLX4_QP_BIT_FPP;
		context->params2 &= ~cpu_to_be32(MLX4_QP_BIT_FPP);
		err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
		context, 0, 0, qp);
		if (err) {

drivers/net/ethernet/mellanox/mlx4/resource_tracker.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -3185,7 +3185,7 @@ static int verify_qp_parameters(struct mlx4_dev *dev,
		optpar = be32_to_cpu((__be32 ) inbox->buf);

		if (slave != mlx4_master_func_num(dev)) {
		qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
		qp_ctx->params2 &= ~cpu_to_be32(MLX4_QP_BIT_FPP);
		/* setting QP rate-limit is disallowed for VFs */
		if (qp_ctx->rate_limit_params)
		return -EPERM;