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Commit bb03efe2 authored by Valentin Rothberg's avatar Valentin Rothberg Committed by Michael Ellerman
Browse files

powerpc/mm/radix: Fix CONFIG_PPC_MMU_STD_64 typo 



It's CONFIG_PPC_STD_MMU_64 not ...
     CONFIG_PPC_MMU_STD_64.

Fixes: 11ffc1cfa4c2 ("powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code")
Signed-off-by: default avatarValentin Rothberg <valentinrothberg@gmail.com>
Reviewed-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 69dfbaeb

arch/powerpc/kernel/mce_power.c

+5 −5
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ void __flush_tlb_power9(unsigned int action) 




/* flush SLBs and reload */

#ifdef CONFIG_PPC_MMU_STD_64

#ifdef CONFIG_PPC_STD_MMU_64

static void flush_and_reload_slb(void)

{

	struct slb_shadow *slb;
@@ -125,7 +125,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) 
	 * reset the error bits whenever we handle them so that at the end

	 * we can check whether we handled all of them or not.

	 * */

#ifdef CONFIG_PPC_MMU_STD_64

#ifdef CONFIG_PPC_STD_MMU_64

	if (dsisr & slb_error_bits) {

		flush_and_reload_slb();

		/* reset error bits */
@@ -157,7 +157,7 @@ static long mce_handle_common_ierror(uint64_t srr1) 
	switch (P7_SRR1_MC_IFETCH(srr1)) {

	case 0:

		break;

#ifdef CONFIG_PPC_MMU_STD_64

#ifdef CONFIG_PPC_STD_MMU_64

	case P7_SRR1_MC_IFETCH_SLB_PARITY:

	case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:

		/* flush and reload SLBs for SLB errors. */
@@ -184,7 +184,7 @@ static long mce_handle_ierror_p7(uint64_t srr1) 


	handled = mce_handle_common_ierror(srr1);



#ifdef CONFIG_PPC_MMU_STD_64

#ifdef CONFIG_PPC_STD_MMU_64

	if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {

		flush_and_reload_slb();

		handled = 1;
@@ -332,7 +332,7 @@ static long mce_handle_ierror_p8(uint64_t srr1) 


	handled = mce_handle_common_ierror(srr1);



#ifdef CONFIG_PPC_MMU_STD_64

#ifdef CONFIG_PPC_STD_MMU_64

	if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {

		flush_and_reload_slb();

		handled = 1;