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Commit ba3f5973 authored Jul 28, 2010 by Mike Frysinger

Blackfin: TWI: clean up the MMR names

The standard short name for control is CTL and not CTRL. Use TWI0_xxx
even on parts that only have one TWI bus to keep things simple. Drop
all the cdef helpers since the bus driver takes care of everything.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

parent ada09172

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

+18 −18

Original line number	Diff line number	Diff line
		@@ -458,22 +458,22 @@

		/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
		#define TWI0_REGBASE 0xFFC01400
		#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
		#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
		#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
		#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
		#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
		#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
		#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
		#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
		#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
		#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */


		/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
		@@ -1319,7 +1319,7 @@
		#define TWI_ENA 0x0080 /* TWI Enable */
		#define SCCB 0x0200 /* SCCB Compatibility Enable */

		/* TWI_SLAVE_CTRL Masks */
		/* TWI_SLAVE_CTL Masks */
		#define SEN 0x0001 /* Slave Enable */
		#define SADD_LEN 0x0002 /* Slave Address Length */
		#define STDVAL 0x0004 /* Slave Transmit Data Valid */
		@@ -1330,7 +1330,7 @@
		#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive) /
		#define GCALL 0x0002 /* General Call Indicator */

		/* TWI_MASTER_CTRL Masks */
		/* TWI_MASTER_CTL Masks */
		#define MEN 0x0001 /* Master Mode Enable */
		#define MADD_LEN 0x0002 /* Master Address Length */
		#define MDIR 0x0004 /* Master Transmit Direction (RX/TX) /

arch/blackfin/mach-bf527/include/mach/defBF52x_base.h

+18 −18

Original line number	Diff line number	Diff line
		@@ -458,22 +458,22 @@

		/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
		#define TWI0_REGBASE 0xFFC01400
		#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
		#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
		#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
		#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
		#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
		#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
		#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
		#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
		#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
		#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */


		/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
		@@ -1328,7 +1328,7 @@
		#define TWI_ENA 0x0080 /* TWI Enable */
		#define SCCB 0x0200 /* SCCB Compatibility Enable */

		/* TWI_SLAVE_CTRL Masks */
		/* TWI_SLAVE_CTL Masks */
		#define SEN 0x0001 /* Slave Enable */
		#define SADD_LEN 0x0002 /* Slave Address Length */
		#define STDVAL 0x0004 /* Slave Transmit Data Valid */
		@@ -1339,7 +1339,7 @@
		#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive) /
		#define GCALL 0x0002 /* General Call Indicator */

		/* TWI_MASTER_CTRL Masks */
		/* TWI_MASTER_CTL Masks */
		#define MEN 0x0001 /* Master Mode Enable */
		#define MADD_LEN 0x0002 /* Master Address Length */
		#define MDIR 0x0004 /* Master Transmit Direction (RX/TX) /

arch/blackfin/mach-bf537/include/mach/defBF534.h

+18 −18

Original line number	Diff line number	Diff line
		@@ -434,22 +434,22 @@

		/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
		#define TWI0_REGBASE 0xFFC01400
		#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
		#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
		#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
		#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
		#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
		#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
		#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
		#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
		#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
		#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */

		/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
		#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
		@@ -1642,7 +1642,7 @@
		#define TWI_ENA 0x0080 /* TWI Enable */
		#define SCCB 0x0200 /* SCCB Compatibility Enable */

		/* TWI_SLAVE_CTRL Masks */
		/* TWI_SLAVE_CTL Masks */
		#define SEN 0x0001 /* Slave Enable */
		#define SADD_LEN 0x0002 /* Slave Address Length */
		#define STDVAL 0x0004 /* Slave Transmit Data Valid */
		@@ -1653,7 +1653,7 @@
		#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive) /
		#define GCALL 0x0002 /* General Call Indicator */

		/* TWI_MASTER_CTRL Masks */
		/* TWI_MASTER_CTL Masks */
		#define MEN 0x0001 /* Master Mode Enable */
		#define MADD_LEN 0x0002 /* Master Address Length */
		#define MDIR 0x0004 /* Master Transmit Direction (RX/TX) /

arch/blackfin/mach-bf538/include/mach/cdefBF538.h

+0 −64

Original line number	Diff line number	Diff line
		@@ -1293,70 +1293,6 @@
		#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
		#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
		#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
		#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
		#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
		#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
		#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
		#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
		#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
		#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
		#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
		#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
		#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
		#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
		#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
		#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
		#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
		#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
		#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
		#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
		#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
		#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
		#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
		#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
		#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
		#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
		#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
		#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
		#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
		#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
		#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
		#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
		#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
		#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
		#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
		#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
		#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
		#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
		#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
		#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
		#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
		#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
		#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
		#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
		#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
		#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
		#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
		#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
		#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
		#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
		#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
		#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
		#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
		#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
		#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
		#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
		#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
		#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
		#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
		#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
		#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
		#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
		#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
		#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
		#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
		#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
		#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
		#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
		#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
		#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)

arch/blackfin/mach-bf538/include/mach/defBF539.h

+7 −7

Original line number	Diff line number	Diff line
		@@ -442,15 +442,15 @@
		/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
		#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
		#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
		#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
		#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
		#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
		#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
		#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
		#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
		#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
		#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
		#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
		#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */
		#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
		#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
		#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
		#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
		@@ -761,15 +761,15 @@
		/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
		#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
		#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
		#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
		#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
		#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
		#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
		#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
		#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
		#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
		#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
		#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
		#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
		#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */
		#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
		#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
		#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
		#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
		@@ -2401,7 +2401,7 @@
		#define XMTSERV 0x0040 /* Transmit FIFO Service */
		#define RCVSERV 0x0080 /* Receive FIFO Service */

		/* TWIx_FIFO_CTRL Masks */
		/* TWIx_FIFO_CTL Masks */
		#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
		#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
		#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */