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Commit b9b77222 authored by Ganapatrao Kulkarni's avatar Ganapatrao Kulkarni Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: Update ThunderX2 implementation defined pmu core events 



Signed-off-by: default avatarGanapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ganapatrao Kulkarni <gklkml16@gmail.com>
Cc: Jan Glauber <jan.glauber@cavium.com>
Cc: Jayachandran C <jnair@caviumnetworks.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <robert.richter@cavium.com>
Cc: Vadim Lomovtsev <vadim.lomovtsev@cavium.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@cavium.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 14a85b1e

tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json

+84 −3
Original line number Diff line number Diff line
@@ -11,6 +11,21 @@ 
    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL",

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD",

    },
@@ -23,10 +38,76 @@ 
    {

        "ArchStdEvent": "L1D_TLB_WR",

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_RD",

    },

    {

        "ArchStdEvent": "L2D_TLB_REFILL_WR",

    },

    {

        "ArchStdEvent": "L2D_TLB_RD",

    },

    {

        "ArchStdEvent": "L2D_TLB_WR",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD",

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR",

    },

    {

        "ArchStdEvent": "MEM_ACCESS_RD",

    },

    {

        "ArchStdEvent": "MEM_ACCESS_WR",

    },

    {

        "ArchStdEvent": "UNALIGNED_LD_SPEC",

    },

    {

        "ArchStdEvent": "UNALIGNED_ST_SPEC",

    },

    {

        "ArchStdEvent": "UNALIGNED_LDST_SPEC",

    },

    {

        "ArchStdEvent": "EXC_UNDEF",

    },

    {

        "ArchStdEvent": "EXC_SVC",

    },

    {

        "ArchStdEvent": "EXC_PABORT",

    },

    {

        "ArchStdEvent": "EXC_DABORT",

    },

    {

        "ArchStdEvent": "EXC_IRQ",

    },

    {

        "ArchStdEvent": "EXC_FIQ",

    },

    {

        "ArchStdEvent": "EXC_SMC",

    },

    {

        "ArchStdEvent": "EXC_HVC",

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT",

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT",

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER",

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ",

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ",

    }

]