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Commit b9500546 authored by Pratyush Anand's avatar Pratyush Anand Committed by Linus Torvalds
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ST SPEAr: PCIE gadget suppport



This is a configurable gadget.  can be configured by configfs interface.
Any IP available at PCIE bus can be programmed to be used by host
controller.It supoorts both INTX and MSI.

By default, the gadget is configured for INTX and SYSRAM1 is mapped to
BAR0 with size 0x1000

Signed-off-by: default avatarPratyush Anand <pratyush.anand@st.com>
Cc: Randy Dunlap <randy.dunlap@oracle.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 45bff2ea
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What:		/config/pcie-gadget
Date:		Feb 2011
KernelVersion:	2.6.37
Contact:	Pratyush Anand <pratyush.anand@st.com>
Description:

	Interface is used to configure selected dual mode PCIe controller
	as device and then program its various registers to configure it
	as a particular device type.
	This interfaces can be used to show spear's PCIe device capability.

	Nodes are only visible when configfs is mounted. To mount configfs
	in /config directory use:
	# mount -t configfs none /config/

	For nth PCIe Device Controller
	/config/pcie-gadget.n/
		link ... used to enable ltssm and read its status.
		int_type ...used to configure and read type of supported
			interrupt
		no_of_msi ... used to configure number of MSI vector needed and
			to read no of MSI granted.
		inta ... write 1 to assert INTA and 0 to de-assert.
		send_msi ... write MSI vector to be sent.
		vendor_id ... used to write and read vendor id (hex)
		device_id ... used to write and read device id (hex)
		bar0_size ... used to write and read bar0_size
		bar0_address ... used to write and read bar0 mapped area in hex.
		bar0_rw_offset ... used to write and read offset of bar0 where
			bar0_data will be written or read.
		bar0_data ... used to write and read data at bar0_rw_offset.
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Spear PCIe Gadget Driver:

Author
=============
Pratyush Anand (pratyush.anand@st.com)

Location
============
driver/misc/spear13xx_pcie_gadget.c

Supported Chip:
===================
SPEAr1300
SPEAr1310

Menuconfig option:
==========================
Device Drivers
	Misc devices
		PCIe gadget support for SPEAr13XX platform
purpose
===========
This driver has several nodes which can be read/written by configfs interface.
Its main purpose is to configure selected dual mode PCIe controller as device
and then program its various registers to configure it as a particular device
type. This driver can be used to show spear's PCIe device capability.

Description of different nodes:
=================================

read behavior of nodes:
------------------------------
link 		:gives ltssm status.
int_type 	:type of supported interrupt
no_of_msi 	:zero if MSI is not enabled by host. A positive value is the
		number of MSI vector granted.
vendor_id	:returns programmed vendor id (hex)
device_id	:returns programmed device id(hex)
bar0_size:	:returns size of bar0 in hex.
bar0_address	:returns address of bar0 mapped area in hex.
bar0_rw_offset	:returns offset of bar0 for which bar0_data will return value.
bar0_data	:returns data at bar0_rw_offset.

write behavior of nodes:
------------------------------
link 		:write UP to enable ltsmm DOWN to disable
int_type	:write interrupt type to be configured and (int_type could be
		INTA, MSI or NO_INT). Select MSI only when you have programmed
		no_of_msi node.
no_of_msi	:number of MSI vector needed.
inta		:write 1 to assert INTA and 0 to de-assert.
send_msi	:write MSI vector to be sent.
vendor_id	:write vendor id(hex) to be programmed.
device_id	:write device id(hex) to be programmed.
bar0_size	:write size of bar0 in hex. default bar0 size is 1000 (hex)
		bytes.
bar0_address	:write	address of bar0 mapped area in hex. (default mapping of
		bar0 is SYSRAM1(E0800000). Always program bar size before bar
		address. Kernel might modify bar size and address for alignment, so
		read back bar size and address after writing to cross check.
bar0_rw_offset	:write offset of bar0 for which	bar0_data will write value.
bar0_data	:write data to be written at bar0_rw_offset.

Node programming example
===========================
Program all PCIe registers in such a way that when this device is connected
to the PCIe host, then host sees this device as 1MB RAM.
#mount -t configfs none /Config
For nth PCIe Device Controller
# cd /config/pcie_gadget.n/
Now you have all the nodes in this directory.
program vendor id as 0x104a
# echo 104A >> vendor_id

program device id as 0xCD80
# echo CD80 >> device_id

program BAR0 size as 1MB
# echo 100000 >> bar0_size

check for programmed bar0 size
# cat bar0_size

Program BAR0 Address as DDR (0x2100000). This is the physical address of
memory, which is to be made visible to PCIe host. Similarly any other peripheral
can also be made visible to PCIe host. E.g., if you program base address of UART
as BAR0 address then when this device will be connected to a host, it will be
visible as UART.
# echo 2100000 >> bar0_address

program interrupt type : INTA
# echo INTA >> int_type

go for link up now.
# echo UP >> link

It will have to be insured that, once link up is done on gadget, then only host
is initialized and start to search PCIe devices on its port.

/*wait till link is up*/
# cat link
wait till it returns UP.

To assert INTA
# echo 1 >> inta

To de-assert INTA
# echo 0 >> inta

if MSI is to be used as interrupt, program no of msi vector needed (say4)
# echo 4 >> no_of_msi

select MSI as interrupt type
# echo MSI >> int_type

go for link up now
# echo UP >> link

wait till link is up
# cat link
An application can repetitively read this node till link is found UP. It can
sleep between two read.

wait till msi is enabled
# cat no_of_msi
Should return 4 (number of requested MSI vector)

to send msi vector 2
# echo 2 >> send_msi
#cd -
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@@ -402,6 +402,16 @@ config DS1682
	  This driver can also be built as a module.  If so, the module
	  This driver can also be built as a module.  If so, the module
	  will be called ds1682.
	  will be called ds1682.


config SPEAR13XX_PCIE_GADGET
	bool "PCIe gadget support for SPEAr13XX platform"
	depends on ARCH_SPEAR13XX
	default n
	help
	 This option enables gadget support for PCIe controller. If
	 board file defines any controller as PCIe endpoint then a sysfs
	 entry will be created for that controller. User can use these
	 sysfs node to configure PCIe EP as per his requirements.

config TI_DAC7512
config TI_DAC7512
	tristate "Texas Instruments DAC7512"
	tristate "Texas Instruments DAC7512"
	depends on SPI && SYSFS
	depends on SPI && SYSFS
+1 −0
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@@ -37,6 +37,7 @@ obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/
obj-$(CONFIG_HMC6352)		+= hmc6352.o
obj-$(CONFIG_HMC6352)		+= hmc6352.o
obj-y				+= eeprom/
obj-y				+= eeprom/
obj-y				+= cb710/
obj-y				+= cb710/
obj-$(CONFIG_SPEAR13XX_PCIE_GADGET)	+= spear13xx_pcie_gadget.o
obj-$(CONFIG_VMWARE_BALLOON)	+= vmw_balloon.o
obj-$(CONFIG_VMWARE_BALLOON)	+= vmw_balloon.o
obj-$(CONFIG_ARM_CHARLCD)	+= arm-charlcd.o
obj-$(CONFIG_ARM_CHARLCD)	+= arm-charlcd.o
obj-$(CONFIG_PCH_PHUB)		+= pch_phub.o
obj-$(CONFIG_PCH_PHUB)		+= pch_phub.o
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File added.

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