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Commit b8fd1f41 authored by Harsh Jain's avatar Harsh Jain Committed by Herbert Xu
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crypto: chcr - Add ctr mode and process large sg entries for cipher



It send multiple WRs to H/W to handle large sg lists. Adds ctr(aes)
and rfc(ctr(aes)) modes.

Signed-off-by: default avatarHarsh Jain <harsh@chelsio.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent d600fc8a
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+646 −140

File changed.

Preview size limit exceeded, changes collapsed.

+25 −1
Original line number Diff line number Diff line
@@ -219,9 +219,26 @@
#define MAX_NK 8
#define CRYPTO_MAX_IMM_TX_PKT_LEN 256
#define MAX_WR_SIZE			512
#define ROUND_16(bytes)		((bytes) & 0xFFFFFFF0)
#define MAX_DSGL_ENT			32
#define MAX_DIGEST_SKB_SGE	(MAX_SKB_FRAGS - 2)
#define MIN_CIPHER_SG			1 /* IV */
#define MIN_AUTH_SG			2 /*IV + AAD*/
#define MIN_GCM_SG			2 /* IV + AAD*/
#define MIN_DIGEST_SG			1 /*Partial Buffer*/
#define MIN_CCM_SG			3 /*IV+AAD+B0*/
#define SPACE_LEFT(len) \
	((MAX_WR_SIZE - WR_MIN_LEN - (len)))

unsigned int sgl_ent_len[] = {0, 0, 16, 24, 40,
				48, 64, 72, 88,
				96, 112, 120, 136,
				144, 160, 168, 184,
				192};
unsigned int dsgl_ent_len[] = {0, 32, 32, 48, 48, 64, 64, 80, 80,
				112, 112, 128, 128, 144, 144, 160, 160,
				192, 192, 208, 208, 224, 224, 240, 240,
				272, 272, 288, 288, 304, 304, 320, 320};

struct algo_param {
	unsigned int auth_mode;
@@ -239,6 +256,14 @@ struct hash_wr_param {
	u64 scmd1;
};

struct cipher_wr_param {
	struct ablkcipher_request *req;
	struct scatterlist *srcsg;
	char *iv;
	int bytes;
	short int snent;
	unsigned short qid;
};
enum {
	AES_KEYLENGTH_128BIT = 128,
	AES_KEYLENGTH_192BIT = 192,
@@ -293,7 +318,6 @@ struct phys_sge_parm {
	unsigned int nents;
	unsigned int obsize;
	unsigned short qid;
	unsigned char align;
};

struct crypto_result {
+0 −1
Original line number Diff line number Diff line
@@ -115,7 +115,6 @@ static int cpl_fw6_pld_handler(struct chcr_dev *dev,
	/* call completion callback with failure status */
	if (req) {
		error_status = chcr_handle_resp(req, input, error_status);
		req->complete(req, error_status);
	} else {
		pr_err("Incorrect request address from the firmware\n");
		return -EFAULT;
+3 −0
Original line number Diff line number Diff line
@@ -53,6 +53,9 @@
#define MAC_ERROR_BIT		0
#define CHK_MAC_ERR_BIT(x)	(((x) >> MAC_ERROR_BIT) & 1)
#define MAX_SALT                4
#define WR_MIN_LEN (sizeof(struct chcr_wr) + \
		    sizeof(struct cpl_rx_phys_dsgl) + \
		    sizeof(struct ulptx_sgl))

#define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)

+16 −3
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@
#define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309    0x06000000
#define CRYPTO_ALG_SUB_TYPE_AEAD_NULL       0x07000000
#define CRYPTO_ALG_SUB_TYPE_CTR             0x08000000
#define CRYPTO_ALG_SUB_TYPE_CTR_RFC3686     0x09000000
#define CRYPTO_ALG_SUB_TYPE_XTS		    0x0a000000
#define CRYPTO_ALG_SUB_TYPE_CBC		    0x0b000000
#define CRYPTO_ALG_TYPE_HMAC (CRYPTO_ALG_TYPE_AHASH |\
			      CRYPTO_ALG_SUB_TYPE_HASH_HMAC)

@@ -150,10 +153,12 @@
/* Aligned to 128 bit boundary */

struct ablk_ctx {
	struct crypto_skcipher *sw_cipher;
	__be32 key_ctx_hdr;
	unsigned int enckey_len;
	u8 key[CHCR_AES_MAX_KEY_LEN];
	unsigned char ciph_mode;
	u8 key[CHCR_AES_MAX_KEY_LEN];
	u8 nonce[4];
	u8 rrkey[AES_MAX_KEY_SIZE];
};
struct chcr_aead_reqctx {
@@ -233,7 +238,14 @@ struct chcr_ahash_req_ctx {

struct chcr_blkcipher_req_ctx {
	struct sk_buff *skb;
	unsigned int dst_nents;
	struct scatterlist srcffwd[2];
	struct scatterlist dstffwd[2];
	struct scatterlist *dstsg;
	struct scatterlist *dst;
	struct scatterlist *newdstsg;
	unsigned int processed;
	unsigned int op;
	short int dst_nents;
	u8 iv[CHCR_MAX_CRYPTO_IV_LEN];
};

@@ -275,5 +287,6 @@ static int chcr_aead_op(struct aead_request *req_base,
			  int size,
			  create_wr_t create_wr_fn);
static inline int get_aead_subtype(struct crypto_aead *aead);

static int chcr_handle_cipher_resp(struct ablkcipher_request *req,
				   unsigned char *input, int err);
#endif /* __CHCR_CRYPTO_H__ */