Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b87fa0fa authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mvpp2-fixes' 



Thomas Petazzoni says:

====================
net: mvpp2: driver fixes

As requested, here is a series of patches containing only bug fixes
for the mvpp2 driver. It is based on the latest "net" branch.

Changes since v1:

 - Fixed a build breakage that occurred when only PATCH 1 was only,
   and not later patches in the series. Was reported by the kbuild
   report on the first submission.

 - Added Tested-by from Marc Zyngier on PATCH 2.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 343eba69 a704bb5c

drivers/net/ethernet/marvell/mvpp2.c

+33 −41
Original line number Original line Diff line number Diff line
@@ -3719,7 +3719,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 
				    dma_addr_t *dma_addr,

				    dma_addr_t *dma_addr,

				    phys_addr_t *phys_addr)

				    phys_addr_t *phys_addr)

{

{

	int cpu = smp_processor_id();

	int cpu = get_cpu();





	*dma_addr = mvpp2_percpu_read(priv, cpu,

	*dma_addr = mvpp2_percpu_read(priv, cpu,

				      MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));

				      MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
@@ -3740,6 +3740,8 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 
		if (sizeof(phys_addr_t) == 8)

		if (sizeof(phys_addr_t) == 8)

			*phys_addr |= (u64)phys_addr_highbits << 32;

			*phys_addr |= (u64)phys_addr_highbits << 32;

	}

	}



	put_cpu();

}

}





/* Free all buffers from the pool */

/* Free all buffers from the pool */
@@ -3920,18 +3922,12 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool) 
	return bm;

	return bm;

}

}





/* Get pool number from a BM cookie */

static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)

{

	return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;

}



/* Release buffer to BM */

/* Release buffer to BM */

static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,

static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,

				     dma_addr_t buf_dma_addr,

				     dma_addr_t buf_dma_addr,

				     phys_addr_t buf_phys_addr)

				     phys_addr_t buf_phys_addr)

{

{

	int cpu = smp_processor_id();

	int cpu = get_cpu();





	if (port->priv->hw_version == MVPP22) {

	if (port->priv->hw_version == MVPP22) {

		u32 val = 0;

		u32 val = 0;
@@ -3958,15 +3954,15 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 
			   MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);

			   MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);

	mvpp2_percpu_write(port->priv, cpu,

	mvpp2_percpu_write(port->priv, cpu,

			   MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);

			   MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);



	put_cpu();

}

}





/* Refill BM pool */

/* Refill BM pool */

static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,

static void mvpp2_pool_refill(struct mvpp2_port *port, int pool,

			      dma_addr_t dma_addr,

			      dma_addr_t dma_addr,

			      phys_addr_t phys_addr)

			      phys_addr_t phys_addr)

{

{

	int pool = mvpp2_bm_cookie_pool_get(bm);



	mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);

	mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);

}

}
@@ -4513,21 +4509,6 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 
	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);

	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);

}

}





/* Obtain BM cookie information from descriptor */

static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,

				 struct mvpp2_rx_desc *rx_desc)

{

	int cpu = smp_processor_id();

	int pool;



	pool = (mvpp2_rxdesc_status_get(port, rx_desc) &

		MVPP2_RXD_BM_POOL_ID_MASK) >>

		MVPP2_RXD_BM_POOL_ID_OFFS;



	return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |

	       ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);

}



/* Tx descriptors helper methods */

/* Tx descriptors helper methods */





/* Get pointer to next Tx descriptor to be processed (send) by HW */

/* Get pointer to next Tx descriptor to be processed (send) by HW */
@@ -4755,7 +4736,7 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 
static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,

static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,

				   struct mvpp2_rx_queue *rxq)

				   struct mvpp2_rx_queue *rxq)

{

{

	int cpu = smp_processor_id();

	int cpu = get_cpu();





	if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)

	if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)

		rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;

		rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
@@ -4763,6 +4744,8 @@ static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 
	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,

			   rxq->pkts_coal);

			   rxq->pkts_coal);



	put_cpu();

}

}





static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)

static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
@@ -4943,7 +4926,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, 
	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);

	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);





	/* Set Rx descriptors queue starting address - indirect access */

	/* Set Rx descriptors queue starting address - indirect access */

	cpu = smp_processor_id();

	cpu = get_cpu();

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);

	if (port->priv->hw_version == MVPP21)

	if (port->priv->hw_version == MVPP21)

		rxq_dma = rxq->descs_dma;

		rxq_dma = rxq->descs_dma;
@@ -4952,6 +4935,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, 
	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);

	put_cpu();





	/* Set Offset */

	/* Set Offset */

	mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);

	mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
@@ -4978,9 +4962,13 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 




	for (i = 0; i < rx_received; i++) {

	for (i = 0; i < rx_received; i++) {

		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);

		struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);

		u32 bm = mvpp2_bm_cookie_build(port, rx_desc);

		u32 status = mvpp2_rxdesc_status_get(port, rx_desc);

		int pool;





		mvpp2_pool_refill(port, bm,

		pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>

			MVPP2_RXD_BM_POOL_ID_OFFS;



		mvpp2_pool_refill(port, pool,

				  mvpp2_rxdesc_dma_addr_get(port, rx_desc),

				  mvpp2_rxdesc_dma_addr_get(port, rx_desc),

				  mvpp2_rxdesc_cookie_get(port, rx_desc));

				  mvpp2_rxdesc_cookie_get(port, rx_desc));

	}

	}
@@ -5010,10 +4998,11 @@ static void mvpp2_rxq_deinit(struct mvpp2_port *port, 
	 * free descriptor number

	 * free descriptor number

	 */

	 */

	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);

	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);

	cpu = smp_processor_id();

	cpu = get_cpu();

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);

	put_cpu();

}

}





/* Create and initialize a Tx queue */

/* Create and initialize a Tx queue */
@@ -5036,7 +5025,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port, 
	txq->last_desc = txq->size - 1;

	txq->last_desc = txq->size - 1;





	/* Set Tx descriptors queue starting address - indirect access */

	/* Set Tx descriptors queue starting address - indirect access */

	cpu = smp_processor_id();

	cpu = get_cpu();

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,

			   txq->descs_dma);

			   txq->descs_dma);
@@ -5061,6 +5050,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port, 
	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,

			   MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |

			   MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |

			   MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));

			   MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));

	put_cpu();





	/* WRR / EJP configuration - indirect access */

	/* WRR / EJP configuration - indirect access */

	tx_port_num = mvpp2_egress_port(port);

	tx_port_num = mvpp2_egress_port(port);
@@ -5131,10 +5121,11 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port, 
	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);

	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);





	/* Set Tx descriptors queue starting address and size */

	/* Set Tx descriptors queue starting address and size */

	cpu = smp_processor_id();

	cpu = get_cpu();

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);

	put_cpu();

}

}





/* Cleanup Tx ports */

/* Cleanup Tx ports */
@@ -5144,7 +5135,7 @@ static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 
	int delay, pending, cpu;

	int delay, pending, cpu;

	u32 val;

	u32 val;





	cpu = smp_processor_id();

	cpu = get_cpu();

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);

	val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);

	val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);

	val |= MVPP2_TXQ_DRAIN_EN_MASK;

	val |= MVPP2_TXQ_DRAIN_EN_MASK;
@@ -5171,6 +5162,7 @@ static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 




	val &= ~MVPP2_TXQ_DRAIN_EN_MASK;

	val &= ~MVPP2_TXQ_DRAIN_EN_MASK;

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);

	mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);

	put_cpu();





	for_each_present_cpu(cpu) {

	for_each_present_cpu(cpu) {

		txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);

		txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
@@ -5418,7 +5410,7 @@ static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 




/* Reuse skb if possible, or allocate a new skb and add it to BM pool */

/* Reuse skb if possible, or allocate a new skb and add it to BM pool */

static int mvpp2_rx_refill(struct mvpp2_port *port,

static int mvpp2_rx_refill(struct mvpp2_port *port,

			   struct mvpp2_bm_pool *bm_pool, u32 bm)

			   struct mvpp2_bm_pool *bm_pool, int pool)

{

{

	dma_addr_t dma_addr;

	dma_addr_t dma_addr;

	phys_addr_t phys_addr;

	phys_addr_t phys_addr;
@@ -5430,7 +5422,7 @@ static int mvpp2_rx_refill(struct mvpp2_port *port, 
	if (!buf)

	if (!buf)

		return -ENOMEM;

		return -ENOMEM;





	mvpp2_pool_refill(port, bm, dma_addr, phys_addr);

	mvpp2_pool_refill(port, pool, dma_addr, phys_addr);





	return 0;

	return 0;

}

}
@@ -5488,7 +5480,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo, 
		unsigned int frag_size;

		unsigned int frag_size;

		dma_addr_t dma_addr;

		dma_addr_t dma_addr;

		phys_addr_t phys_addr;

		phys_addr_t phys_addr;

		u32 bm, rx_status;

		u32 rx_status;

		int pool, rx_bytes, err;

		int pool, rx_bytes, err;

		void *data;

		void *data;
@@ -5500,8 +5492,8 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo, 
		phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);

		phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);

		data = (void *)phys_to_virt(phys_addr);

		data = (void *)phys_to_virt(phys_addr);





		bm = mvpp2_bm_cookie_build(port, rx_desc);

		pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>

		pool = mvpp2_bm_cookie_pool_get(bm);

			MVPP2_RXD_BM_POOL_ID_OFFS;

		bm_pool = &port->priv->bm_pools[pool];

		bm_pool = &port->priv->bm_pools[pool];





		/* In case of an error, release the requested buffer pointer

		/* In case of an error, release the requested buffer pointer
@@ -5514,7 +5506,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo, 
			dev->stats.rx_errors++;

			dev->stats.rx_errors++;

			mvpp2_rx_error(port, rx_desc);

			mvpp2_rx_error(port, rx_desc);

			/* Return the buffer to the pool */

			/* Return the buffer to the pool */

			mvpp2_pool_refill(port, bm, dma_addr, phys_addr);

			mvpp2_pool_refill(port, pool, dma_addr, phys_addr);

			continue;

			continue;

		}

		}
@@ -5529,7 +5521,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo, 
			goto err_drop_frame;

			goto err_drop_frame;

		}

		}





		err = mvpp2_rx_refill(port, bm_pool, bm);

		err = mvpp2_rx_refill(port, bm_pool, pool);

		if (err) {

		if (err) {

			netdev_err(port->dev, "failed to refill BM pools\n");

			netdev_err(port->dev, "failed to refill BM pools\n");

			goto err_drop_frame;

			goto err_drop_frame;