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Commit b814b074 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Chris Wilson
Browse files

drm/i915/guc: Simplify programming of GUC_SHIM_CONTROL 



We can program GUC_SHIM_CONTROL register with all expected
bits without use of extra macro defined in fwif.h

v2: rebased without pre-prod code
v3: fixed typo

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171103151816.62048-4-michal.wajdeczko@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent e6843363

drivers/gpu/drm/i915/i915_guc_reg.h

+0 −7
Original line number Original line Diff line number Diff line
@@ -102,13 +102,6 @@ 
#define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)

#define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)

#define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)

#define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)





#define GUC_SHIM_CONTROL_VALUE	(GUC_DISABLE_SRAM_INIT_TO_ZEROES	| \

				 GUC_ENABLE_READ_CACHE_LOGIC		| \

				 GUC_ENABLE_MIA_CACHING			| \

				 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	| \

				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \

				 GUC_ENABLE_MIA_CLOCK_GATING)



#define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)

#define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)

#define   GUC_SEND_TRIGGER		  (1<<0)

#define   GUC_SEND_TRIGGER		  (1<<0)

drivers/gpu/drm/i915/intel_guc_fw.c

+7 −2
Original line number Original line Diff line number Diff line
@@ -101,8 +101,13 @@ static void guc_prepare_xfer(struct intel_guc *guc) 
{

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct drm_i915_private *dev_priv = guc_to_i915(guc);





	/* Enable MIA caching. GuC clock gating is disabled. */

	/* Must program this register before loading the ucode with DMA */

	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);

	I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |

				     GUC_ENABLE_READ_CACHE_LOGIC |

				     GUC_ENABLE_MIA_CACHING |

				     GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |

				     GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |

				     GUC_ENABLE_MIA_CLOCK_GATING);





	if (IS_GEN9_LP(dev_priv))

	if (IS_GEN9_LP(dev_priv))

		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);

		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);