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Commit b80b8d7a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlx5e-xdp' 



Tariq Toukan says:

====================
mlx5e XDP support

This series adds XDP support in mlx5e driver.
This includes the use cases: XDP_DROP, XDP_PASS, and XDP_TX.

Single stream performance tests show 16.5 Mpps for XDP_DROP,
and 12.4 Mpps for XDP_TX, with nice scalability for multiple streams/rings.

This rate of XDP_DROP is lower than the 32 Mpps we got in previous
implementation, when Striding RQ was used.

We moved to non-Striding RQ, as some XDP_TX requirements (like headroom,
packet-per-page) cannot be satisfied with the current Striding RQ HW,
and we decided to fully support both DROP/TX.

Few directions are considered in order to enable the faster rate for XDP_DROP,
e.g a possibility for users to enable Striding RQ so they choose optimized
XDP_DROP on the price of partial XDP_TX functionality, or some HW changes.

Series generated against net-next commit:
cf714ac1 'ipvlan: Fix dependency issue'

Thanks,
Tariq

V2:
* patch 8:
 - when XDP_TX fails, call mlx5e_page_release and drop the packet.
 - update xdp_tx counter within mlx5e_xmit_xdp_frame.
   (mlx5e_xmit_xdp_frame return value becomes obsolete, change it to void)
 - drop the packet for unknown XDP return code.
* patch 9:
 - use a boolean for xdp_doorbell in SQ struct, instead of dragging it
   throughout the functions calls.
 - handle doorbell and counters within mlx5e_xmit_xdp_frame.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f9616c35 35b510e2

drivers/net/ethernet/mellanox/mlx5/core/en.h

+56 −13
Original line number Original line Diff line number Diff line
@@ -65,6 +65,8 @@ 
#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3

#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3

#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6

#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6





#define MLX5_RX_HEADROOM NET_SKB_PAD



#define MLX5_MPWRQ_LOG_STRIDE_SIZE		6  /* >= 6, HW restriction */

#define MLX5_MPWRQ_LOG_STRIDE_SIZE		6  /* >= 6, HW restriction */

#define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS	8  /* >= 6, HW restriction */

#define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS	8  /* >= 6, HW restriction */

#define MLX5_MPWRQ_LOG_WQE_SZ			18

#define MLX5_MPWRQ_LOG_WQE_SZ			18
@@ -99,6 +101,18 @@ 
#define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */

#define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */

#define MLX5E_SQ_BF_BUDGET             16

#define MLX5E_SQ_BF_BUDGET             16





#define MLX5E_ICOSQ_MAX_WQEBBS \

	(DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))



#define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)

#define MLX5E_XDP_IHS_DS_COUNT \

	DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)

#define MLX5E_XDP_TX_DS_COUNT \

	(MLX5E_XDP_IHS_DS_COUNT + \

	 (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)

#define MLX5E_XDP_TX_WQEBBS \

	DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)



#define MLX5E_NUM_MAIN_GROUPS 9

#define MLX5E_NUM_MAIN_GROUPS 9





static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)

static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
@@ -302,10 +316,20 @@ struct mlx5e_page_cache { 
struct mlx5e_rq {

struct mlx5e_rq {

	/* data path */

	/* data path */

	struct mlx5_wq_ll      wq;

	struct mlx5_wq_ll      wq;

	u32                    wqe_sz;



	struct sk_buff       **skb;

	union {

	struct mlx5e_mpw_info *wqe_info;

		struct mlx5e_dma_info *dma_info;

		struct {

			struct mlx5e_mpw_info *info;

			void                  *mtt_no_align;

			void                  *mtt_no_align;

			u32                    mtt_offset;

		} mpwqe;

	};

	struct {

		u8             page_order;

		u32            wqe_sz;    /* wqe data buffer size */

		u8             map_dir;   /* dma map direction */

	} buff;

	__be32                 mkey_be;

	__be32                 mkey_be;





	struct device         *pdev;

	struct device         *pdev;
@@ -321,9 +345,9 @@ struct mlx5e_rq { 




	unsigned long          state;

	unsigned long          state;

	int                    ix;

	int                    ix;

	u32                    mpwqe_mtt_offset;





	struct mlx5e_rx_am     am; /* Adaptive Moderation */

	struct mlx5e_rx_am     am; /* Adaptive Moderation */

	struct bpf_prog       *xdp_prog;





	/* control */

	/* control */

	struct mlx5_wq_ctrl    wq_ctrl;

	struct mlx5_wq_ctrl    wq_ctrl;
@@ -370,11 +394,17 @@ enum { 
	MLX5E_SQ_STATE_BF_ENABLE,

	MLX5E_SQ_STATE_BF_ENABLE,

};

};





struct mlx5e_ico_wqe_info {

struct mlx5e_sq_wqe_info {

	u8  opcode;

	u8  opcode;

	u8  num_wqebbs;

	u8  num_wqebbs;

};

};





enum mlx5e_sq_type {

	MLX5E_SQ_TXQ,

	MLX5E_SQ_ICO,

	MLX5E_SQ_XDP

};



struct mlx5e_sq {

struct mlx5e_sq {

	/* data path */

	/* data path */
@@ -392,10 +422,20 @@ struct mlx5e_sq { 




	struct mlx5e_cq            cq;

	struct mlx5e_cq            cq;





	/* pointers to per packet info: write@xmit, read@completion */

	/* pointers to per tx element info: write@xmit, read@completion */

	union {

		struct {

			struct sk_buff           **skb;

			struct sk_buff           **skb;

			struct mlx5e_sq_dma       *dma_fifo;

			struct mlx5e_sq_dma       *dma_fifo;

			struct mlx5e_tx_wqe_info  *wqe_info;

			struct mlx5e_tx_wqe_info  *wqe_info;

		} txq;

		struct mlx5e_sq_wqe_info *ico_wqe;

		struct {

			struct mlx5e_sq_wqe_info  *wqe_info;

			struct mlx5e_dma_info     *di;

			bool                       doorbell;

		} xdp;

	} db;





	/* read only */

	/* read only */

	struct mlx5_wq_cyc         wq;

	struct mlx5_wq_cyc         wq;
@@ -417,8 +457,8 @@ struct mlx5e_sq { 
	struct mlx5_uar            uar;

	struct mlx5_uar            uar;

	struct mlx5e_channel      *channel;

	struct mlx5e_channel      *channel;

	int                        tc;

	int                        tc;

	struct mlx5e_ico_wqe_info *ico_wqe_info;

	u32                        rate_limit;

	u32                        rate_limit;

	u8                         type;

} ____cacheline_aligned_in_smp;

} ____cacheline_aligned_in_smp;





static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)

static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
@@ -434,8 +474,10 @@ enum channel_flags { 
struct mlx5e_channel {

struct mlx5e_channel {

	/* data path */

	/* data path */

	struct mlx5e_rq            rq;

	struct mlx5e_rq            rq;

	struct mlx5e_sq            xdp_sq;

	struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];

	struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];

	struct mlx5e_sq            icosq;   /* internal control operations */

	struct mlx5e_sq            icosq;   /* internal control operations */

	bool                       xdp;

	struct napi_struct         napi;

	struct napi_struct         napi;

	struct device             *pdev;

	struct device             *pdev;

	struct net_device         *netdev;

	struct net_device         *netdev;
@@ -617,6 +659,7 @@ struct mlx5e_priv { 
	/* priv data path fields - start */

	/* priv data path fields - start */

	struct mlx5e_sq            **txq_to_sq_map;

	struct mlx5e_sq            **txq_to_sq_map;

	int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];

	int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];

	struct bpf_prog *xdp_prog;

	/* priv data path fields - end */

	/* priv data path fields - end */





	unsigned long              state;

	unsigned long              state;
@@ -663,7 +706,7 @@ void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); 
int mlx5e_napi_poll(struct napi_struct *napi, int budget);

int mlx5e_napi_poll(struct napi_struct *napi, int budget);

bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);

bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);

int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);

int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);

void mlx5e_free_tx_descs(struct mlx5e_sq *sq);

void mlx5e_free_sq_descs(struct mlx5e_sq *sq);





void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,

void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,

			bool recycle);

			bool recycle);
@@ -764,7 +807,7 @@ static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) 




static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)

static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)

{

{

	return rq->mpwqe_mtt_offset +

	return rq->mpwqe.mtt_offset +

		wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);

		wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);

}

}