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Commit b7f720d6 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
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MIPS: Alchemy: Clean up GPIO registers and accessors 



remove au_readl/au_writel, remove the predefined GPIO1/2 KSEG1 register
addresses and fix the fallout in all boards and drivers.

This also fixes a bug in the mtx-1_wdt driver which was introduced by
commit 6ea8115b
("Convert mtx1 wdt to be a platform device and use generic GPIO API")
before this patch mtx-1_wdt only modified GPIO215, the patch then
used the gpio resource information as bit index into the GPIO2 register
but the conversion to the GPIO API didn't realize that.
With this patch the drivers original behaviour is restored and GPIO15
is left alone.

Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
Cc: Florian Fainelli <florian@openwrt.org>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: linux-watchdog@vger.kernel.org
Cc: Wim Van Sebroeck <wim@iguana.be>
Patchwork: https://patchwork.linux-mips.org/patch/2381/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5d4ddcb4

arch/mips/alchemy/devboards/pb1000/board_setup.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ void __init board_setup(void) 


	/* Set AUX clock to 12 MHz * 8 = 96 MHz */

	au_writel(8, SYS_AUXPLL);

	au_writel(0, SYS_PINSTATERD);

	alchemy_gpio1_input_enable();

	udelay(100);



#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)

arch/mips/alchemy/devboards/pb1500/board_setup.c

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ void __init board_setup(void) 
	sys_clksrc = sys_freqctrl = pin_func = 0;

	/* Set AUX clock to 12 MHz * 8 = 96 MHz */

	au_writel(8, SYS_AUXPLL);

	au_writel(0, SYS_PINSTATERD);

	alchemy_gpio1_input_enable();

	udelay(100);



	/* GPIO201 is input for PCMCIA card detect */

arch/mips/alchemy/mtx-1/board_setup.c

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ void __init board_setup(void) 
	au_writel(SYS_PF_NI2, SYS_PINFUNC);



	/* Initialize GPIO */

	au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);

	au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);

	alchemy_gpio_direction_output(0, 0);	/* Disable M66EN (PCI 66MHz) */

	alchemy_gpio_direction_output(3, 1);	/* Disable PCI CLKRUN# */

	alchemy_gpio_direction_output(1, 1);	/* Enable EXT_IO3 */

arch/mips/alchemy/mtx-1/platform.c

+2 −2
Original line number Diff line number Diff line
@@ -53,8 +53,8 @@ static struct platform_device mtx1_button = { 


static struct resource mtx1_wdt_res[] = {

	[0] = {

		.start	= 15,

		.end	= 15,

		.start	= 215,

		.end	= 215,

		.name	= "mtx1-wdt-gpio",

		.flags	= IORESOURCE_IRQ,

	}

arch/mips/include/asm/mach-au1x00/au1000.h

+2 −25
Original line number Diff line number Diff line
@@ -702,7 +702,9 @@ enum soc_au1200_ints { 
#define AU1000_UART1_PHYS_ADDR		0x11200000 /* 0234 */

#define AU1000_UART2_PHYS_ADDR		0x11300000 /* 0 */

#define AU1000_UART3_PHYS_ADDR		0x11400000 /* 0123 */

#define AU1500_GPIO2_PHYS_ADDR		0x11700000 /* 1234 */

#define AU1000_IC1_PHYS_ADDR		0x11800000 /* 01234 */

#define AU1000_SYS_PHYS_ADDR		0x11900000 /* 01234 */

#define AU1000_DMA_PHYS_ADDR		0x14002000 /* 012 */

#define AU1550_DBDMA_PHYS_ADDR		0x14002000 /* 34 */

#define AU1550_DBDMA_CONF_PHYS_ADDR	0x14003000 /* 34 */
@@ -717,7 +719,6 @@ enum soc_au1200_ints { 
#define	IRDA_PHYS_ADDR		0x10300000

#define	SSI0_PHYS_ADDR		0x11600000

#define	SSI1_PHYS_ADDR		0x11680000

#define	SYS_PHYS_ADDR		0x11900000

#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL

#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL

#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL
@@ -730,8 +731,6 @@ enum soc_au1200_ints { 
#define	STATIC_MEM_PHYS_ADDR	0x14001000

#define	USBH_PHYS_ADDR		0x10100000

#define PCI_PHYS_ADDR		0x14005000

#define GPIO2_PHYS_ADDR		0x11700000

#define	SYS_PHYS_ADDR		0x11900000

#define PCI_MEM_PHYS_ADDR	0x400000000ULL

#define PCI_IO_PHYS_ADDR	0x500000000ULL

#define PCI_CONFIG0_PHYS_ADDR	0x600000000ULL
@@ -750,8 +749,6 @@ enum soc_au1200_ints { 
#define	IRDA_PHYS_ADDR		0x10300000

#define	SSI0_PHYS_ADDR		0x11600000

#define	SSI1_PHYS_ADDR		0x11680000

#define GPIO2_PHYS_ADDR		0x11700000

#define	SYS_PHYS_ADDR		0x11900000

#define LCD_PHYS_ADDR		0x15000000

#define PCMCIA_IO_PHYS_ADDR	0xF00000000ULL

#define PCMCIA_ATTR_PHYS_ADDR	0xF40000000ULL
@@ -765,8 +762,6 @@ enum soc_au1200_ints { 
#define	STATIC_MEM_PHYS_ADDR	0x14001000

#define	USBH_PHYS_ADDR		0x14020000

#define PCI_PHYS_ADDR		0x14005000

#define GPIO2_PHYS_ADDR		0x11700000

#define	SYS_PHYS_ADDR		0x11900000

#define PE_PHYS_ADDR		0x14008000

#define PSC0_PHYS_ADDR		0x11A00000

#define PSC1_PHYS_ADDR		0x11B00000
@@ -790,8 +785,6 @@ enum soc_au1200_ints { 
#define CIM_PHYS_ADDR		0x14004000

#define USBM_PHYS_ADDR		0x14020000

#define	USBH_PHYS_ADDR		0x14020100

#define GPIO2_PHYS_ADDR		0x11700000

#define	SYS_PHYS_ADDR		0x11900000

#define PSC0_PHYS_ADDR	 	0x11A00000

#define PSC1_PHYS_ADDR	 	0x11B00000

#define LCD_PHYS_ADDR		0x15000000
@@ -1359,22 +1352,6 @@ enum soc_au1200_ints { 
#define SYS_PINFUNC_S1B 	(1 << 2)

#endif



#define SYS_TRIOUTRD		0xB1900100

#define SYS_TRIOUTCLR		0xB1900100

#define SYS_OUTPUTRD		0xB1900108

#define SYS_OUTPUTSET		0xB1900108

#define SYS_OUTPUTCLR		0xB190010C

#define SYS_PINSTATERD		0xB1900110

#define SYS_PININPUTEN		0xB1900110



/* GPIO2, Au1500, Au1550 only */

#define GPIO2_BASE		0xB1700000

#define GPIO2_DIR		(GPIO2_BASE + 0)

#define GPIO2_OUTPUT		(GPIO2_BASE + 8)

#define GPIO2_PINSTATE		(GPIO2_BASE + 0xC)

#define GPIO2_INTENABLE 	(GPIO2_BASE + 0x10)

#define GPIO2_ENABLE		(GPIO2_BASE + 0x14)



/* Power Management */

#define SYS_SCRATCH0		0xB1900018

#define SYS_SCRATCH1		0xB190001C