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Commit b7aee517 authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Paul Mundt
Browse files

sh: se7780 PCI support. 



Add support for the SH7780 PCIC on the Solution Engine 7780,
missing from the previous board-support patch.

Signed-off-by: default avatarNobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent b7576230

arch/sh/drivers/pci/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -19,3 +19,4 @@ obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o 
obj-$(CONFIG_SH_TITAN)			+= ops-titan.o

obj-$(CONFIG_SH_LANDISK)		+= ops-landisk.o

obj-$(CONFIG_SH_LBOX_RE2)		+= ops-lboxre2.o fixups-lboxre2.o

obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)	+= ops-se7780.o fixups-se7780.o

arch/sh/drivers/pci/fixups-se7780.c

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/*

 * arch/sh/drivers/pci/fixups-se7780.c

 *

 * HITACHI UL Solution Engine 7780  PCI fixups

 *

 * Copyright (C) 2003  Lineo uSolutions, Inc.

 * Copyright (C) 2004 - 2006  Paul Mundt

 * Copyright (C) 2006  Nobuhiro Iwamatsu

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/pci.h>

#include "pci-sh4.h"

#include <asm/io.h>



int pci_fixup_pcic(void)

{

	ctrl_outl(0x00000001, SH7780_PCI_VCR2);



	/* Enable all interrupts, so we know what to fix */

	pci_write_reg(0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(0x0000380F, SH7780_PCIAINTM);



	/* Set up standard PCI config registers */

	ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));

	ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));

	ctrl_outb(  0x00, PCI_REG(SH7780_PCIPIF));

	ctrl_outb(  0x00, PCI_REG(SH7780_PCISUB));

	ctrl_outb(  0x06, PCI_REG(SH7780_PCIBCC));

	ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));

	ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));



	pci_write_reg(0x08000000, SH7780_PCIMBAR0);     /* PCI */

	pci_write_reg(0x08000000, SH7780_PCILAR0);     /* SHwy */

	pci_write_reg(0x07F00001, SH7780_PCILSR);      /* size 128M w/ MBAR */



	pci_write_reg(0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(0x00000000, SH7780_PCILAR1);

	pci_write_reg(0x00000000, SH7780_PCILSR1);



	pci_write_reg(0xAB000801, SH7780_PCIIBAR);



	/*

	 * Set the MBR so PCI address is one-to-one with window,

	 * meaning all calls go straight through... use ifdef to

	 * catch erroneous assumption.

	 */

	pci_write_reg(0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */



	/* Set IOBR for window containing area specified in pci.h */

	pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);

	pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);



	pci_write_reg(0xA5000C01, SH7780_PCICR);



	return 0;

}

arch/sh/drivers/pci/ops-se7780.c

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/*

 * linux/arch/sh/drivers/pci/ops-se7780.c

 *

 * Copyright (C) 2006  Nobuhiro Iwamatsu

 *

 * PCI initialization for the Hitachi UL Solution Engine 7780SE03

 *

 * May be copied or modified under the terms of the GNU General Public

 * License.  See linux/COPYING for more information.

 */

#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/init.h>

#include <linux/delay.h>

#include <linux/pci.h>

#include <asm/se7780.h>

#include <asm/io.h>

#include "pci-sh4.h"



/*

 * IDSEL = AD16  PCI slot

 * IDSEL = AD17  PCI slot

 * IDSEL = AD18  Serial ATA Controller (Silicon Image SiL3512A)

 * IDSEL = AD19  USB Host Controller (NEC uPD7210100A)

 */



/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */

static char se7780_irq_tab[4][16] __initdata = {

	/* INTA */

	{ 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },

	/* INTB */

	{ 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },

	/* INTC */

	{ 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },

	/* INTD */

	{ 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },

};



int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)

{

       return se7780_irq_tab[pin-1][slot];

}



static struct resource se7780_io_resource = {

	.name	= "SH7780_IO",

	.start	= 0x2000,

	.end	= 0x2000 + SH7780_PCI_IO_SIZE - 1,

	.flags	= IORESOURCE_IO

};



static struct resource se7780_mem_resource = {

	.name	= "SH7780_mem",

	.start	= SH7780_PCI_MEMORY_BASE,

	.end	= SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,

	.flags	= IORESOURCE_MEM

};



extern struct pci_ops se7780_pci_ops;



struct pci_channel board_pci_channels[] = {

	{ &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },

	{ NULL, NULL, NULL, 0, 0 },

};

EXPORT_SYMBOL(board_pci_channels);



static struct sh4_pci_address_map se7780_pci_map = {

	.window0	= {

		.base	= SH7780_CS2_BASE_ADDR,

		.size	= 0x04000000,

	},

	.flags  = SH4_PCIC_NO_RESET,

};



int __init pcibios_init_platform(void)

{

	printk("SH7780 PCI: Finished initialization of the PCI controller\n");



	/*

	 * FPGA PCISEL register initialize

	 *

	 *  CPU  || SLOT1 | SLOT2 | S-ATA | USB

	 *  -------------------------------------

	 *  INTA || INTA  | INTD  |  --   | INTB

	 *  -------------------------------------

	 *  INTB || INTB  | INTA  |  --   | INTC

	 *  -------------------------------------

	 *  INTC || INTC  | INTB  | INTA  |  --

	 *  -------------------------------------

	 *  INTD || INTD  | INTC  |  --   | INTA

	 *  -------------------------------------

	 */

	ctrl_outw(0x0013, FPGA_PCI_INTSEL1);

	ctrl_outw(0xE402, FPGA_PCI_INTSEL2);



	return sh7780_pcic_init(&se7780_pci_map);

}