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Commit b5affb01 authored by Bob Liu's avatar Bob Liu
Browse files

blackfin: add bf60x to current framework 



This patch added bf60x to current blackfin kernel framework.

Signed-off-by: default avatarBob Liu <lliubbo@gmail.com>
parent 22a82628

arch/blackfin/Kconfig

+20 −5
Original line number Diff line number Diff line
@@ -226,6 +226,12 @@ config BF561 
	help

	  BF561 Processor Support.



config BF609

	bool "BF609"

	select CLKDEV_LOOKUP

	help

	  BF609 Processor Support.



endchoice



config SMP
@@ -251,27 +257,27 @@ config HOTPLUG_CPU 


config BF_REV_MIN

	int

	default 0 if (BF51x || BF52x || (BF54x && !BF54xM))

	default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x

	default 2 if (BF537 || BF536 || BF534)

	default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)

	default 4 if (BF538 || BF539)



config BF_REV_MAX

	int

	default 2 if (BF51x || BF52x || (BF54x && !BF54xM))

	default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x

	default 3 if (BF537 || BF536 || BF534 || BF54xM)

	default 5 if (BF561 || BF538 || BF539)

	default 6 if (BF533 || BF532 || BF531)



choice

	prompt "Silicon Rev"

	default BF_REV_0_0 if (BF51x || BF52x)

	default BF_REV_0_0 if (BF51x || BF52x || BF60x)

	default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))

	default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)



config BF_REV_0_0

	bool "0.0"

	depends on (BF51x || BF52x || (BF54x && !BF54xM))

	depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)



config BF_REV_0_1

	bool "0.1"
@@ -350,6 +356,7 @@ source "arch/blackfin/mach-bf561/Kconfig" 
source "arch/blackfin/mach-bf537/Kconfig"

source "arch/blackfin/mach-bf538/Kconfig"

source "arch/blackfin/mach-bf548/Kconfig"

source "arch/blackfin/mach-bf609/Kconfig"



menu "Board customizations"
@@ -379,6 +386,12 @@ config BOOT_LOAD 
	  memory region is used to capture NULL pointer references as well

	  as some core kernel functions.



config PHY_RAM_BASE_ADDRESS

	hex "Physical RAM Base"

	default 0x0

	help

	  set BF609 FPGA physical SRAM base address



config ROM_BASE

	hex "Kernel ROM Base"

	depends on ROMKERNEL
@@ -1051,7 +1064,7 @@ endchoice 
config BFIN_L2_DCACHEABLE

	bool "Enable DCACHE for L2 SRAM"

	depends on BFIN_DCACHE

	depends on (BF54x || BF561) && !SMP

	depends on (BF54x || BF561 || BF60x) && !SMP

	default n

choice

	prompt "L2 SRAM DCACHE policy"
@@ -1077,6 +1090,7 @@ config MPU 
comment "Asynchronous Memory Configuration"



menu "EBIU_AMGCTL Global Control"

	depends on !BF60x

config C_AMCKEN

	bool "Enable CLKOUT"

	default y
@@ -1127,6 +1141,7 @@ endchoice 
endmenu



menu "EBIU_AMBCTL Control"

	depends on !BF60x

config BANK_0

	hex "Bank 0 (AMBCTL0.L)"

	default 0x7BB0

arch/blackfin/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ machine-$(CONFIG_BF548M) := bf548 
machine-$(CONFIG_BF549)  := bf548

machine-$(CONFIG_BF549M) := bf548

machine-$(CONFIG_BF561)  := bf561

machine-$(CONFIG_BF609)  := bf609

MACHINE := $(machine-y)

export MACHINE
@@ -86,6 +87,7 @@ cpu-$(CONFIG_BF548M) := bf548m 
cpu-$(CONFIG_BF549)  := bf549

cpu-$(CONFIG_BF549M) := bf549m

cpu-$(CONFIG_BF561)  := bf561

cpu-$(CONFIG_BF609)  := bf609



rev-$(CONFIG_BF_REV_0_0)  := 0.0

rev-$(CONFIG_BF_REV_0_1)  := 0.1

arch/blackfin/configs/BF609-EZKIT_defconfig

0 → 100644
+153 −0
Original line number Diff line number Diff line 
CONFIG_EXPERIMENTAL=y

CONFIG_SYSVIPC=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_LOG_BUF_SHIFT=14

CONFIG_BLK_DEV_INITRD=y

CONFIG_EXPERT=y

# CONFIG_ELF_CORE is not set

# CONFIG_FUTEX is not set

# CONFIG_SIGNALFD is not set

# CONFIG_TIMERFD is not set

# CONFIG_EVENTFD is not set

# CONFIG_AIO is not set

CONFIG_SLAB=y

CONFIG_MMAP_ALLOW_UNINITIALIZED=y

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

# CONFIG_LBDAF is not set

# CONFIG_BLK_DEV_BSG is not set

# CONFIG_IOSCHED_DEADLINE is not set

# CONFIG_IOSCHED_CFQ is not set

CONFIG_PREEMPT_VOLUNTARY=y

CONFIG_BF609=y

CONFIG_PINT1_ASSIGN=0x01010000

CONFIG_PINT2_ASSIGN=0x07000101

CONFIG_PINT3_ASSIGN=0x02020303

CONFIG_HIGH_RES_TIMERS=y

CONFIG_IP_CHECKSUM_L1=y

CONFIG_SYSCALL_TAB_L1=y

CONFIG_CPLB_SWITCH_TAB_L1=y

# CONFIG_APP_STACK_L1 is not set

# CONFIG_BFIN_INS_LOWOVERHEAD is not set

CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0

CONFIG_BINFMT_FLAT=y

CONFIG_BINFMT_ZFLAT=y

# CONFIG_SUSPEND is not set

CONFIG_CPU_FREQ=y

CONFIG_CPU_FREQ_GOV_POWERSAVE=y

CONFIG_CPU_FREQ_GOV_ONDEMAND=y

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_INET=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

CONFIG_IP_PNP_RARP=y

# CONFIG_IPV6 is not set

CONFIG_NETFILTER=y

CONFIG_CAN=y

CONFIG_CAN_BFIN=y

CONFIG_IRDA=y

CONFIG_IRTTY_SIR=y

# CONFIG_WIRELESS is not set

CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"

CONFIG_FW_LOADER=m

CONFIG_MTD=y

CONFIG_MTD_CMDLINE_PARTS=y

CONFIG_MTD_CHAR=y

CONFIG_MTD_CFI=y

CONFIG_MTD_CFI_INTELEXT=y

CONFIG_MTD_CFI_STAA=y

CONFIG_MTD_COMPLEX_MAPPINGS=y

CONFIG_MTD_BFIN_BF60x=y

CONFIG_MTD_M25P80=y

CONFIG_MTD_UBI=m

CONFIG_SCSI=y

CONFIG_BLK_DEV_SD=y

CONFIG_NETDEVICES=y

# CONFIG_NET_VENDOR_BROADCOM is not set

# CONFIG_NET_VENDOR_CHELSIO is not set

# CONFIG_NET_VENDOR_INTEL is not set

# CONFIG_NET_VENDOR_MARVELL is not set

# CONFIG_NET_VENDOR_MICREL is not set

# CONFIG_NET_VENDOR_MICROCHIP is not set

# CONFIG_NET_VENDOR_NATSEMI is not set

# CONFIG_NET_VENDOR_SEEQ is not set

# CONFIG_NET_VENDOR_SMSC is not set

CONFIG_STMMAC_ETH=y

CONFIG_STMMAC_IEEE1588=y

# CONFIG_WLAN is not set

# CONFIG_INPUT_MOUSEDEV is not set

CONFIG_INPUT_EVDEV=y

# CONFIG_INPUT_KEYBOARD is not set

# CONFIG_INPUT_MOUSE is not set

CONFIG_INPUT_MISC=y

CONFIG_INPUT_BFIN_ROTARY=y

# CONFIG_SERIO is not set

# CONFIG_LEGACY_PTYS is not set

CONFIG_BFIN_SIMPLE_TIMER=m

CONFIG_BFIN_LINKPORT=y

# CONFIG_DEVKMEM is not set

CONFIG_SERIAL_BFIN=y

CONFIG_SERIAL_BFIN_CONSOLE=y

CONFIG_SERIAL_BFIN_UART0=y

# CONFIG_HW_RANDOM is not set

CONFIG_I2C=y

CONFIG_I2C_CHARDEV=y

CONFIG_I2C_BLACKFIN_TWI=y

CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100

CONFIG_SPI=y

CONFIG_SPI_BFIN6XX=y

CONFIG_GPIOLIB=y

CONFIG_GPIO_SYSFS=y

# CONFIG_HWMON is not set

CONFIG_WATCHDOG=y

CONFIG_BFIN_WDT=y

CONFIG_SOUND=m

CONFIG_SND=m

CONFIG_SND_MIXER_OSS=m

CONFIG_SND_PCM_OSS=m

# CONFIG_SND_DRIVERS is not set

# CONFIG_SND_SPI is not set

# CONFIG_SND_USB is not set

CONFIG_SND_SOC=m

CONFIG_SND_BF6XX_I2S=m

CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m

CONFIG_SND_SOC_ALL_CODECS=m

CONFIG_USB=y

CONFIG_USB_MUSB_HDRC=y

CONFIG_USB_MUSB_BLACKFIN=y

CONFIG_USB_STORAGE=y

CONFIG_USB_GADGET=y

CONFIG_USB_GADGET_MUSB_HDRC=y

CONFIG_USB_ZERO=y

CONFIG_MMC=y

CONFIG_SDH_BFIN=y

# CONFIG_IOMMU_SUPPORT is not set

CONFIG_EXT2_FS=y

# CONFIG_DNOTIFY is not set

CONFIG_MSDOS_FS=y

CONFIG_VFAT_FS=y

CONFIG_JFFS2_FS=m

CONFIG_UBIFS_FS=m

CONFIG_NFS_FS=m

CONFIG_NFS_V3=y

CONFIG_NLS_CODEPAGE_437=y

CONFIG_NLS_ISO8859_1=y

CONFIG_DEBUG_FS=y

CONFIG_DEBUG_SHIRQ=y

CONFIG_DETECT_HUNG_TASK=y

CONFIG_DEBUG_INFO=y

CONFIG_FRAME_POINTER=y

# CONFIG_FTRACE is not set

CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y

CONFIG_EARLY_PRINTK=y

CONFIG_CPLB_INFO=y

CONFIG_BFIN_PSEUDODBG_INSNS=y

CONFIG_CRYPTO_HMAC=y

CONFIG_CRYPTO_MD4=y

CONFIG_CRYPTO_MD5=y

CONFIG_CRYPTO_ARC4=y

# CONFIG_CRYPTO_ANSI_CPRNG is not set

arch/blackfin/include/asm/bfin-global.h

+5 −0
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu); 


extern unsigned long get_cclk(void);

extern unsigned long get_sclk(void);

#ifdef CONFIG_BF60x

extern unsigned long get_sclk0(void);

extern unsigned long get_sclk1(void);

extern unsigned long get_dramclk(void);

#endif

extern unsigned long sclk_to_usecs(unsigned long sclk);

extern unsigned long usecs_to_sclk(unsigned long usecs);

arch/blackfin/include/asm/bfin_dma.h

+79 −5
Original line number Diff line number Diff line
@@ -15,12 +15,55 @@ 
#define DMAEN			0x0001	/* DMA Channel Enable */

#define WNR				0x0002	/* Channel Direction (W/R*) */

#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */

#define PSIZE_8			0x00000000	/* Transfer Word Size = 16 */



#ifdef CONFIG_BF60x



#define PSIZE_16		0x00000010	/* Transfer Word Size = 16 */

#define PSIZE_32		0x00000020	/* Transfer Word Size = 32 */

#define PSIZE_64		0x00000030	/* Transfer Word Size = 32 */

#define WDSIZE_16		0x00000100	/* Transfer Word Size = 16 */

#define WDSIZE_32		0x00000200	/* Transfer Word Size = 32 */

#define WDSIZE_64		0x00000300	/* Transfer Word Size = 32 */

#define WDSIZE_128		0x00000400	/* Transfer Word Size = 32 */

#define WDSIZE_256		0x00000500	/* Transfer Word Size = 32 */

#define DMA2D			0x04000000	/* DMA Mode (2D/1D*) */

#define RESTART			0x00000004	/* DMA Buffer Clear SYNC */

#define DI_EN_X			0x00100000	/* Data Interrupt Enable in X count */

#define DI_EN_Y			0x00200000	/* Data Interrupt Enable in Y count */

#define DI_EN_P			0x00300000	/* Data Interrupt Enable in Peripheral */

#define DI_EN			DI_EN_X		/* Data Interrupt Enable */

#define NDSIZE_0		0x00000000	/* Next Descriptor Size = 1 */

#define NDSIZE_1		0x00010000	/* Next Descriptor Size = 2 */

#define NDSIZE_2		0x00020000	/* Next Descriptor Size = 3 */

#define NDSIZE_3		0x00030000	/* Next Descriptor Size = 4 */

#define NDSIZE_4		0x00040000	/* Next Descriptor Size = 5 */

#define NDSIZE_5		0x00050000	/* Next Descriptor Size = 6 */

#define NDSIZE_6		0x00060000	/* Next Descriptor Size = 7 */

#define NDSIZE			0x00070000	/* Next Descriptor Size */

#define NDSIZE_OFFSET		16		/* Next Descriptor Size Offset */

#define DMAFLOW_LIST		0x00004000	/* Descriptor List Mode */

#define DMAFLOW_LARGE		DMAFLOW_LIST

#define DMAFLOW_ARRAY		0x00005000	/* Descriptor Array Mode */

#define DMAFLOW_LIST_DEMAND	0x00006000	/* Descriptor Demand List Mode */

#define DMAFLOW_ARRAY_DEMAND	0x00007000	/* Descriptor Demand Array Mode */

#define DMA_RUN_DFETCH		0x00000100	/* DMA Channel Running Indicator (DFETCH) */

#define DMA_RUN			0x00000200	/* DMA Channel Running Indicator */

#define DMA_RUN_WAIT_TRIG	0x00000300	/* DMA Channel Running Indicator (WAIT TRIG) */

#define DMA_RUN_WAIT_ACK	0x00000400	/* DMA Channel Running Indicator (WAIT ACK) */



#else



#define PSIZE_16		0x0000	/* Transfer Word Size = 16 */

#define PSIZE_32		0x0000	/* Transfer Word Size = 32 */

#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */

#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */

#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */

#define RESTART			0x0020	/* DMA Buffer Clear */

#define DI_SEL			0x0040	/* Data Interrupt Timing Select */

#define DI_EN			0x0080	/* Data Interrupt Enable */

#define DI_EN_X			0x00C0	/* Data Interrupt Enable in X count*/

#define DI_EN_Y			0x0080	/* Data Interrupt Enable in Y count*/

#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */

#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */

#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
@@ -32,18 +75,26 @@ 
#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */

#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */

#define NDSIZE			0x0f00	/* Next Descriptor Size */

#define DMAFLOW			0x7000	/* Flow Control */

#define DMAFLOW_STOP	0x0000	/* Stop Mode */

#define DMAFLOW_AUTO	0x1000	/* Autobuffer Mode */

#define NDSIZE_OFFSET		8	/* Next Descriptor Size Offset */

#define DMAFLOW_ARRAY	0x4000	/* Descriptor Array Mode */

#define DMAFLOW_SMALL	0x6000	/* Small Model Descriptor List Mode */

#define DMAFLOW_LARGE	0x7000	/* Large Model Descriptor List Mode */

#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */

#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */



#endif

#define DMAFLOW			0x7000	/* Flow Control */

#define DMAFLOW_STOP	0x0000	/* Stop Mode */

#define DMAFLOW_AUTO	0x1000	/* Autobuffer Mode */



/* DMA_IRQ_STATUS Masks */

#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */

#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */

#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */

#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */

#ifdef CONFIG_BF60x

#define DMA_PIRQ		0x0004	/* DMA Peripheral Error Interrupt Status */

#else

#define DMA_PIRQ		0

#endif



/*

 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -57,6 +108,26 @@ 
struct bfin_dma_regs {

	u32 next_desc_ptr;

	u32 start_addr;

#ifdef CONFIG_BF60x

	u32 cfg;

	u32 x_count;

	u32 x_modify;

	u32 y_count;

	u32 y_modify;

	u32 pad1;

	u32 pad2;

	u32 curr_desc_ptr;

	u32 prev_desc_ptr;

	u32 curr_addr;

	u32 irq_status;

	u32 curr_x_count;

	u32 curr_y_count;

	u32 pad3;

	u32 bw_limit_count;

	u32 curr_bw_limit_count;

	u32 bw_monitor_count;

	u32 curr_bw_monitor_count;

#else

	__BFP(config);

	u32 __pad0;

	__BFP(x_count);
@@ -71,8 +142,10 @@ struct bfin_dma_regs { 
	u32 __pad1;

	__BFP(curr_y_count);

	u32 __pad2;

#endif

};



#ifndef CONFIG_BF60x

/*

 * bfin handshake mdma registers layout

 */
@@ -85,6 +158,7 @@ struct bfin_hmdma_regs { 
	__BFP(ecount);

	__BFP(bcount);

};

#endif



#undef __BFP