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Commit b572b24c authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville
Browse files

ath9k: remove dummy PCI "retry timeout" fix 



Remove the PCI retry timeout code as that was just taken from ipw2100
due to historical reasons but in reality its a no-op, additionally its
simply incorrect as each PCI devices has its own custom PCI configuration
space on PCI config space >= 0x40. Not to mention we were trying to write
0 to a place that already has 0 on it.

Cc: Matthew Garrett <mjg59@srcf.ucam.org>
Cc: Ben Cahill <ben.m.cahill@intel.com>
Cc: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Tested-by: default avatarAdel Gadllah <adel.gadllah@gmail.com>
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 4ed96f04

drivers/net/wireless/ath9k/pci.c

+0 −18
Original line number Diff line number Diff line
@@ -87,7 +87,6 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	struct ath_softc *sc;

	struct ieee80211_hw *hw;

	u8 csz;

	u32 val;

	int ret = 0;

	struct ath_hw *ah;
@@ -134,14 +133,6 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 


	pci_set_master(pdev);



	/*

	 * Disable the RETRY_TIMEOUT register (0x41) to keep

	 * PCI Tx retries from interfering with C3 CPU state.

	 */

	pci_read_config_dword(pdev, 0x40, &val);

	if ((val & 0x0000ff00) != 0)

		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);



	ret = pci_request_region(pdev, 0, "ath9k");

	if (ret) {

		dev_err(&pdev->dev, "PCI memory region reserve error\n");
@@ -253,21 +244,12 @@ static int ath_pci_resume(struct pci_dev *pdev) 
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);

	struct ath_wiphy *aphy = hw->priv;

	struct ath_softc *sc = aphy->sc;

	u32 val;

	int err;



	err = pci_enable_device(pdev);

	if (err)

		return err;

	pci_restore_state(pdev);

	/*

	 * Suspend/Resume resets the PCI configuration space, so we have to

	 * re-disable the RETRY_TIMEOUT register (0x41) to keep

	 * PCI Tx retries from interfering with C3 CPU state

	 */

	pci_read_config_dword(pdev, 0x40, &val);

	if ((val & 0x0000ff00) != 0)

		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);



	/* Enable LED */

	ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,