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Commit b4eac546 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'sunxi-drm-for-4.9' of... 

Merge tag 'sunxi-drm-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next

Allwinner DRM changes for 4.9

This tag adds the support of a new SoC to sun4i-drm (the Allwinner A33),
and the usual few fixes and enhancements

* tag 'sunxi-drm-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  drm/sun4i: add missing header dependencies
  drm/sun4i: Add a DRC driver
  drm/sun4i: backend: Handle the SAT
  drm/sun4i: support A33 tcon
  drm/sun4i: support TCONs without channel 1
  drm/sun4i: Clear encoder->bridge if a bridge is not found
  drm/sun4i: rgb: add missing calls to drm_panel_{prepare,unprepare}
  drm/sun4i: Remove redundant dev_err call in sun4i_tcon_init_regmap()
  drm/sun4i: Add bridge support
  drm/sun4i: Move panel retrieval in RGB connector
  drm/sun4i: Store TCON's device structure pointer
parents 1f8ee720 0c3ff44c

Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

+41 −2
Original line number Diff line number Diff line
@@ -26,13 +26,14 @@ TCON 
The TCON acts as a timing controller for RGB, LVDS and TV interfaces.



Required properties:

 - compatible: value should be "allwinner,sun5i-a13-tcon".

 - compatible: value must be either:

   * allwinner,sun5i-a13-tcon

   * allwinner,sun8i-a33-tcon

 - reg: base address and size of memory-mapped region

 - interrupts: interrupt associated to this IP

 - clocks: phandles to the clocks feeding the TCON. Three are needed:

   - 'ahb': the interface clocks

   - 'tcon-ch0': The clock driving the TCON channel 0

   - 'tcon-ch1': The clock driving the TCON channel 1

 - resets: phandles to the reset controllers driving the encoder

   - "lcd": the reset line for the TCON channel 0
@@ -49,6 +50,33 @@ Required properties: 
  second the block connected to the TCON channel 1 (usually the TV

  encoder)



On the A13, there is one more clock required:

   - 'tcon-ch1': The clock driving the TCON channel 1



DRC

---



The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs

(A31, A23, A33), allows to dynamically adjust pixel

brightness/contrast based on histogram measurements for LCD content

adaptive backlight control.





Required properties:

  - compatible: value must be one of:

    * allwinner,sun8i-a33-drc

  - reg: base address and size of the memory-mapped region.

  - interrupts: interrupt associated to this IP

  - clocks: phandles to the clocks feeding the DRC

    * ahb: the DRC interface clock

    * mod: the DRC module clock

    * ram: the DRC DRAM clock

  - clock-names: the clock names mentioned above

  - resets: phandles to the reset line driving the DRC



- ports: A ports node with endpoint definitions as defined in

  Documentation/devicetree/bindings/media/video-interfaces.txt. The

  first port should be the input endpoints, the second one the outputs



Display Engine Backend

----------------------
@@ -59,6 +87,7 @@ system. 
Required properties:

  - compatible: value must be one of:

    * allwinner,sun5i-a13-display-backend

    * allwinner,sun8i-a33-display-backend

  - reg: base address and size of the memory-mapped region.

  - clocks: phandles to the clocks feeding the frontend and backend

    * ahb: the backend interface clock
@@ -71,6 +100,14 @@ Required properties: 
  Documentation/devicetree/bindings/media/video-interfaces.txt. The

  first port should be the input endpoints, the second one the output



On the A33, some additional properties are required:

  - reg needs to have an additional region corresponding to the SAT

  - reg-names need to be set, with "be" and "sat"

  - clocks and clock-names need to have a phandle to the SAT bus

    clocks, whose name will be "sat"

  - resets and reset-names need to have a phandle to the SAT bus

    resets, whose name will be "sat"



Display Engine Frontend

-----------------------
@@ -80,6 +117,7 @@ deinterlacing and color space conversion. 
Required properties:

  - compatible: value must be one of:

    * allwinner,sun5i-a13-display-frontend

    * allwinner,sun8i-a33-display-frontend

  - reg: base address and size of the memory-mapped region.

  - interrupts: interrupt associated to this IP

  - clocks: phandles to the clocks feeding the frontend and backend
@@ -104,6 +142,7 @@ extra node. 
Required properties:

  - compatible: value must be one of:

    * allwinner,sun5i-a13-display-engine

    * allwinner,sun8i-a33-display-engine



  - allwinner,pipelines: list of phandle to the display engine

    frontends available.

drivers/gpu/drm/sun4i/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -9,5 +9,5 @@ sun4i-tcon-y += sun4i_dotclock.o 


obj-$(CONFIG_DRM_SUN4I)		+= sun4i-drm.o sun4i-tcon.o

obj-$(CONFIG_DRM_SUN4I)		+= sun4i_backend.o



obj-$(CONFIG_DRM_SUN4I)		+= sun6i_drc.o

obj-$(CONFIG_DRM_SUN4I)		+= sun4i_tv.o

drivers/gpu/drm/sun4i/sun4i_backend.c

+61 −0
Original line number Diff line number Diff line
@@ -217,6 +217,51 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, 
}

EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);



static int sun4i_backend_init_sat(struct device *dev) {

	struct sun4i_backend *backend = dev_get_drvdata(dev);

	int ret;



	backend->sat_reset = devm_reset_control_get(dev, "sat");

	if (IS_ERR(backend->sat_reset)) {

		dev_err(dev, "Couldn't get the SAT reset line\n");

		return PTR_ERR(backend->sat_reset);

	}



	ret = reset_control_deassert(backend->sat_reset);

	if (ret) {

		dev_err(dev, "Couldn't deassert the SAT reset line\n");

		return ret;

	}



	backend->sat_clk = devm_clk_get(dev, "sat");

	if (IS_ERR(backend->sat_clk)) {

		dev_err(dev, "Couldn't get our SAT clock\n");

		ret = PTR_ERR(backend->sat_clk);

		goto err_assert_reset;

	}



	ret = clk_prepare_enable(backend->sat_clk);

	if (ret) {

		dev_err(dev, "Couldn't enable the SAT clock\n");

		return ret;

	}



	return 0;



err_assert_reset:

	reset_control_assert(backend->sat_reset);

	return ret;

}



static int sun4i_backend_free_sat(struct device *dev) {

	struct sun4i_backend *backend = dev_get_drvdata(dev);



	clk_disable_unprepare(backend->sat_clk);

	reset_control_assert(backend->sat_reset);



	return 0;

}



static struct regmap_config sun4i_backend_regmap_config = {

	.reg_bits	= 32,

	.val_bits	= 32,
@@ -291,6 +336,15 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, 
	}

	clk_prepare_enable(backend->ram_clk);



	if (of_device_is_compatible(dev->of_node,

				    "allwinner,sun8i-a33-display-backend")) {

		ret = sun4i_backend_init_sat(dev);

		if (ret) {

			dev_err(dev, "Couldn't init SAT resources\n");

			goto err_disable_ram_clk;

		}

	}



	/* Reset the registers */

	for (i = 0x800; i < 0x1000; i += 4)

		regmap_write(backend->regs, i, 0);
@@ -306,6 +360,8 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, 


	return 0;



err_disable_ram_clk:

	clk_disable_unprepare(backend->ram_clk);

err_disable_mod_clk:

	clk_disable_unprepare(backend->mod_clk);

err_disable_bus_clk:
@@ -320,6 +376,10 @@ static void sun4i_backend_unbind(struct device *dev, struct device *master, 
{

	struct sun4i_backend *backend = dev_get_drvdata(dev);



	if (of_device_is_compatible(dev->of_node,

				    "allwinner,sun8i-a33-display-backend"))

		sun4i_backend_free_sat(dev);



	clk_disable_unprepare(backend->ram_clk);

	clk_disable_unprepare(backend->mod_clk);

	clk_disable_unprepare(backend->bus_clk);
@@ -345,6 +405,7 @@ static int sun4i_backend_remove(struct platform_device *pdev) 


static const struct of_device_id sun4i_backend_of_table[] = {

	{ .compatible = "allwinner,sun5i-a13-display-backend" },

	{ .compatible = "allwinner,sun8i-a33-display-backend" },

	{ }

};

MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);

drivers/gpu/drm/sun4i/sun4i_backend.h

+3 −0
Original line number Diff line number Diff line
@@ -146,6 +146,9 @@ struct sun4i_backend { 
	struct clk		*bus_clk;

	struct clk		*mod_clk;

	struct clk		*ram_clk;



	struct clk		*sat_clk;

	struct reset_control	*sat_reset;

};



void sun4i_backend_apply_color_correction(struct sun4i_backend *backend);

drivers/gpu/drm/sun4i/sun4i_dotclock.c

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/regmap.h>



#include "sun4i_tcon.h"

#include "sun4i_dotclock.h"



struct sun4i_dclk {

	struct clk_hw	hw;