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Commit b492b874 authored by Akshay Bhat's avatar Akshay Bhat Committed by Shawn Guo
Browse files

ARM: dts: imx6q-b850v3: Update display clock source 



The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.

Signed-off-by: default avatarAkshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7532c98f

arch/arm/boot/dts/imx6q-b850v3.dts

+11 −4
Original line number Diff line number Diff line
@@ -53,11 +53,18 @@ 
	};

};



&ldb {

&clks {

	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,

				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,

			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,

			  <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,

				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;

};



&ldb {

	fsl,dual-channel;

	status = "okay";