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Commit b38f41eb authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: unify VM size handling of Vega10 with older generation 



One function to rule them all.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0410c5e5

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+13 −21
Original line number Diff line number Diff line
@@ -2573,21 +2573,6 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) 
		return ((bits + 3) / 2);

}



/**

 * amdgpu_vm_set_fragment_size - adjust fragment size in PTE

 *

 * @adev: amdgpu_device pointer

 * @fragment_size_default: the default fragment size if it's set auto

 */

void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,

				 uint32_t fragment_size_default)

{

	if (amdgpu_vm_fragment_size == -1)

		adev->vm_manager.fragment_size = fragment_size_default;

	else

		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;

}



/**

 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size

 *
@@ -2595,22 +2580,29 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, 
 * @vm_size: the default vm size if it's set auto

 */

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,

			   uint32_t fragment_size_default)

			   uint32_t fragment_size_default, unsigned max_level)

{

	/* adjust vm size firstly */

	if (amdgpu_vm_size != -1)

	/* adjust vm size first, but only for two level setups for now */

	if (amdgpu_vm_size != -1 && max_level == 1)

		vm_size = amdgpu_vm_size;



	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;

	adev->vm_manager.num_level = max_level;



	/* block size depends on vm size */

	if (amdgpu_vm_block_size == -1)

	/* block size depends on vm size and hw setup*/

	if (adev->vm_manager.num_level > 1)

		/* Use fixed block_size for multi level page tables */

		adev->vm_manager.block_size = 9;

	else if (amdgpu_vm_block_size == -1)

		adev->vm_manager.block_size =

			amdgpu_vm_get_block_size(vm_size);

	else

		adev->vm_manager.block_size = amdgpu_vm_block_size;



	amdgpu_vm_set_fragment_size(adev, fragment_size_default);

	if (amdgpu_vm_fragment_size == -1)

		adev->vm_manager.fragment_size = fragment_size_default;

	else

		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;



	DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",

		 vm_size, adev->vm_manager.block_size,

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+1 −3
Original line number Diff line number Diff line
@@ -324,10 +324,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 
							 uint64_t addr);

void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,

		      struct amdgpu_bo_va *bo_va);

void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,

				 uint32_t fragment_size_default);

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,

			   uint32_t fragment_size_default);

			   uint32_t fragment_size_default, unsigned max_level);

int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);

bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,

				  struct amdgpu_job *job);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+1 −2
Original line number Diff line number Diff line
@@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle) 
	if (r)

		return r;



	amdgpu_vm_adjust_size(adev, 64, 9);

	amdgpu_vm_adjust_size(adev, 64, 9, 1);



	adev->mc.mc_mask = 0xffffffffffULL;
@@ -877,7 +877,6 @@ static int gmc_v6_0_sw_init(void *handle) 
	 * amdkfd will use VMIDs 8-15

	 */

	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;

	adev->vm_manager.num_level = 1;

	amdgpu_vm_manager_init(adev);



	/* base offset of vram pages */

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+1 −2
Original line number Diff line number Diff line
@@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle) 
	 * Currently set to 4GB ((1 << 20) 4k pages).

	 * Max GPUVM size for cayman and SI is 40 bits.

	 */

	amdgpu_vm_adjust_size(adev, 64, 9);

	amdgpu_vm_adjust_size(adev, 64, 9, 1);



	/* Set the internal MC address mask

	 * This is the max address of the GPU's
@@ -1026,7 +1026,6 @@ static int gmc_v7_0_sw_init(void *handle) 
	 * amdkfd will use VMIDs 8-15

	 */

	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;

	adev->vm_manager.num_level = 1;

	amdgpu_vm_manager_init(adev);



	/* base offset of vram pages */

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+1 −2
Original line number Diff line number Diff line
@@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle) 
	 * Currently set to 4GB ((1 << 20) 4k pages).

	 * Max GPUVM size for cayman and SI is 40 bits.

	 */

	amdgpu_vm_adjust_size(adev, 64, 9);

	amdgpu_vm_adjust_size(adev, 64, 9, 1);



	/* Set the internal MC address mask

	 * This is the max address of the GPU's
@@ -1123,7 +1123,6 @@ static int gmc_v8_0_sw_init(void *handle) 
	 * amdkfd will use VMIDs 8-15

	 */

	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;

	adev->vm_manager.num_level = 1;

	amdgpu_vm_manager_init(adev);



	/* base offset of vram pages */