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Commit b25b33ac authored by Sukadev Bhattiprolu's avatar Sukadev Bhattiprolu Committed by Michael Ellerman
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powerpc/powernv/vas: Define helpers to init window context 



Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.

Signed-off-by: default avatarSukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 180fe15a

arch/powerpc/platforms/powernv/vas-window.c

+299 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/mutex.h>

#include <linux/slab.h>

#include <linux/io.h>

#include <linux/log2.h>



#include "vas.h"
@@ -186,6 +187,304 @@ int map_winctx_mmio_bars(struct vas_window *window) 
	return 0;

}



/*

 * Reset all valid registers in the HV and OS/User Window Contexts for

 * the window identified by @window.

 *

 * NOTE: We cannot really use a for loop to reset window context. Not all

 *	 offsets in a window context are valid registers and the valid

 *	 registers are not sequential. And, we can only write to offsets

 *	 with valid registers.

 */

void reset_window_regs(struct vas_window *window)

{

	write_hvwc_reg(window, VREG(LPID), 0ULL);

	write_hvwc_reg(window, VREG(PID), 0ULL);

	write_hvwc_reg(window, VREG(XLATE_MSR), 0ULL);

	write_hvwc_reg(window, VREG(XLATE_LPCR), 0ULL);

	write_hvwc_reg(window, VREG(XLATE_CTL), 0ULL);

	write_hvwc_reg(window, VREG(AMR), 0ULL);

	write_hvwc_reg(window, VREG(SEIDR), 0ULL);

	write_hvwc_reg(window, VREG(FAULT_TX_WIN), 0ULL);

	write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL);

	write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), 0ULL);

	write_hvwc_reg(window, VREG(PSWID), 0ULL);

	write_hvwc_reg(window, VREG(LFIFO_BAR), 0ULL);

	write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), 0ULL);

	write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), 0ULL);

	write_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL);

	write_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL);

	write_hvwc_reg(window, VREG(LRX_WCRED), 0ULL);

	write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);

	write_hvwc_reg(window, VREG(TX_WCRED), 0ULL);

	write_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);

	write_hvwc_reg(window, VREG(LFIFO_SIZE), 0ULL);

	write_hvwc_reg(window, VREG(WINCTL), 0ULL);

	write_hvwc_reg(window, VREG(WIN_STATUS), 0ULL);

	write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), 0ULL);

	write_hvwc_reg(window, VREG(TX_RSVD_BUF_COUNT), 0ULL);

	write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_CTL), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_PID), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_LPID), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_TID), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), 0ULL);

	write_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL);



	/* Skip read-only registers: NX_UTIL and NX_UTIL_SE */



	/*

	 * The send and receive window credit adder registers are also

	 * accessible from HVWC and have been initialized above. We don't

	 * need to initialize from the OS/User Window Context, so skip

	 * following calls:

	 *

	 *	write_uwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);

	 *	write_uwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);

	 */

}



/*

 * Initialize window context registers related to Address Translation.

 * These registers are common to send/receive windows although they

 * differ for user/kernel windows. As we resolve the TODOs we may

 * want to add fields to vas_winctx and move the initialization to

 * init_vas_winctx_regs().

 */

static void init_xlate_regs(struct vas_window *window, bool user_win)

{

	u64 lpcr, val;



	/*

	 * MSR_TA, MSR_US are false for both kernel and user.

	 * MSR_DR and MSR_PR are false for kernel.

	 */

	val = 0ULL;

	val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1);

	val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1);

	if (user_win) {

		val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1);

		val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1);

	}

	write_hvwc_reg(window, VREG(XLATE_MSR), val);



	lpcr = mfspr(SPRN_LPCR);

	val = 0ULL;

	/*

	 * NOTE: From Section 5.7.8.1 Segment Lookaside Buffer of the

	 *	 Power ISA, v3.0B, Page size encoding is 0 = 4KB, 5 = 64KB.

	 *

	 * NOTE: From Section 1.3.1, Address Translation Context of the

	 *	 Nest MMU Workbook, LPCR_SC should be 0 for Power9.

	 */

	val = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5);

	val = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL);

	val = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC);

	val = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0);

	write_hvwc_reg(window, VREG(XLATE_LPCR), val);



	/*

	 * Section 1.3.1 (Address translation Context) of NMMU workbook.

	 *	0b00	Hashed Page Table mode

	 *	0b01	Reserved

	 *	0b10	Radix on HPT

	 *	0b11	Radix on Radix

	 */

	val = 0ULL;

	val = SET_FIELD(VAS_XLATE_MODE, val, radix_enabled() ? 3 : 2);

	write_hvwc_reg(window, VREG(XLATE_CTL), val);



	/*

	 * TODO: Can we mfspr(AMR) even for user windows?

	 */

	val = 0ULL;

	val = SET_FIELD(VAS_AMR, val, mfspr(SPRN_AMR));

	write_hvwc_reg(window, VREG(AMR), val);



	val = 0ULL;

	val = SET_FIELD(VAS_SEIDR, val, 0);

	write_hvwc_reg(window, VREG(SEIDR), val);

}



/*

 * Initialize Reserved Send Buffer Count for the send window. It involves

 * writing to the register, reading it back to confirm that the hardware

 * has enough buffers to reserve. See section 1.3.1.2.1 of VAS workbook.

 *

 * Since we can only make a best-effort attempt to fulfill the request,

 * we don't return any errors if we cannot.

 *

 * TODO: Reserved (aka dedicated) send buffers are not supported yet.

 */

static void init_rsvd_tx_buf_count(struct vas_window *txwin,

				struct vas_winctx *winctx)

{

	write_hvwc_reg(txwin, VREG(TX_RSVD_BUF_COUNT), 0ULL);

}



/*

 * init_winctx_regs()

 *	Initialize window context registers for a receive window.

 *	Except for caching control and marking window open, the registers

 *	are initialized in the order listed in Section 3.1.4 (Window Context

 *	Cache Register Details) of the VAS workbook although they don't need

 *	to be.

 *

 * Design note: For NX receive windows, NX allocates the FIFO buffer in OPAL

 *	(so that it can get a large contiguous area) and passes that buffer

 *	to kernel via device tree. We now write that buffer address to the

 *	FIFO BAR. Would it make sense to do this all in OPAL? i.e have OPAL

 *	write the per-chip RX FIFO addresses to the windows during boot-up

 *	as a one-time task? That could work for NX but what about other

 *	receivers?  Let the receivers tell us the rx-fifo buffers for now.

 */

int init_winctx_regs(struct vas_window *window, struct vas_winctx *winctx)

{

	u64 val;

	int fifo_size;



	reset_window_regs(window);



	val = 0ULL;

	val = SET_FIELD(VAS_LPID, val, winctx->lpid);

	write_hvwc_reg(window, VREG(LPID), val);



	val = 0ULL;

	val = SET_FIELD(VAS_PID_ID, val, winctx->pidr);

	write_hvwc_reg(window, VREG(PID), val);



	init_xlate_regs(window, winctx->user_win);



	val = 0ULL;

	val = SET_FIELD(VAS_FAULT_TX_WIN, val, 0);

	write_hvwc_reg(window, VREG(FAULT_TX_WIN), val);



	/* In PowerNV, interrupts go to HV. */

	write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL);



	val = 0ULL;

	val = SET_FIELD(VAS_HV_INTR_SRC_RA, val, winctx->irq_port);

	write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), val);



	val = 0ULL;

	val = SET_FIELD(VAS_PSWID_EA_HANDLE, val, winctx->pswid);

	write_hvwc_reg(window, VREG(PSWID), val);



	write_hvwc_reg(window, VREG(SPARE1), 0ULL);

	write_hvwc_reg(window, VREG(SPARE2), 0ULL);

	write_hvwc_reg(window, VREG(SPARE3), 0ULL);



	/*

	 * NOTE: VAS expects the FIFO address to be copied into the LFIFO_BAR

	 *	 register as is - do NOT shift the address into VAS_LFIFO_BAR

	 *	 bit fields! Ok to set the page migration select fields -

	 *	 VAS ignores the lower 10+ bits in the address anyway, because

	 *	 the minimum FIFO size is 1K?

	 *

	 * See also: Design note in function header.

	 */

	val = __pa(winctx->rx_fifo);

	val = SET_FIELD(VAS_PAGE_MIGRATION_SELECT, val, 0);

	write_hvwc_reg(window, VREG(LFIFO_BAR), val);



	val = 0ULL;

	val = SET_FIELD(VAS_LDATA_STAMP, val, winctx->data_stamp);

	write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), val);



	val = 0ULL;

	val = SET_FIELD(VAS_LDMA_TYPE, val, winctx->dma_type);

	val = SET_FIELD(VAS_LDMA_FIFO_DISABLE, val, winctx->fifo_disable);

	write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), val);



	write_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL);

	write_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL);

	write_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL);



	val = 0ULL;

	val = SET_FIELD(VAS_LRX_WCRED, val, winctx->wcreds_max);

	write_hvwc_reg(window, VREG(LRX_WCRED), val);



	val = 0ULL;

	val = SET_FIELD(VAS_TX_WCRED, val, winctx->wcreds_max);

	write_hvwc_reg(window, VREG(TX_WCRED), val);



	write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);

	write_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);



	fifo_size = winctx->rx_fifo_size / 1024;



	val = 0ULL;

	val = SET_FIELD(VAS_LFIFO_SIZE, val, ilog2(fifo_size));

	write_hvwc_reg(window, VREG(LFIFO_SIZE), val);



	/* Update window control and caching control registers last so

	 * we mark the window open only after fully initializing it and

	 * pushing context to cache.

	 */



	write_hvwc_reg(window, VREG(WIN_STATUS), 0ULL);



	init_rsvd_tx_buf_count(window, winctx);



	/* for a send window, point to the matching receive window */

	val = 0ULL;

	val = SET_FIELD(VAS_LRX_WIN_ID, val, winctx->rx_win_id);

	write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), val);



	write_hvwc_reg(window, VREG(SPARE4), 0ULL);



	val = 0ULL;

	val = SET_FIELD(VAS_NOTIFY_DISABLE, val, winctx->notify_disable);

	val = SET_FIELD(VAS_INTR_DISABLE, val, winctx->intr_disable);

	val = SET_FIELD(VAS_NOTIFY_EARLY, val, winctx->notify_early);

	val = SET_FIELD(VAS_NOTIFY_OSU_INTR, val, winctx->notify_os_intr_reg);

	write_hvwc_reg(window, VREG(LNOTIFY_CTL), val);



	val = 0ULL;

	val = SET_FIELD(VAS_LNOTIFY_PID, val, winctx->lnotify_pid);

	write_hvwc_reg(window, VREG(LNOTIFY_PID), val);



	val = 0ULL;

	val = SET_FIELD(VAS_LNOTIFY_LPID, val, winctx->lnotify_lpid);

	write_hvwc_reg(window, VREG(LNOTIFY_LPID), val);



	val = 0ULL;

	val = SET_FIELD(VAS_LNOTIFY_TID, val, winctx->lnotify_tid);

	write_hvwc_reg(window, VREG(LNOTIFY_TID), val);



	val = 0ULL;

	val = SET_FIELD(VAS_LNOTIFY_MIN_SCOPE, val, winctx->min_scope);

	val = SET_FIELD(VAS_LNOTIFY_MAX_SCOPE, val, winctx->max_scope);

	write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), val);



	/* Skip read-only registers NX_UTIL and NX_UTIL_SE */



	write_hvwc_reg(window, VREG(SPARE5), 0ULL);

	write_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL);

	write_hvwc_reg(window, VREG(SPARE6), 0ULL);



	/* Finally, push window context to memory and... */

	val = 0ULL;

	val = SET_FIELD(VAS_PUSH_TO_MEM, val, 1);

	write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val);



	/* ... mark the window open for business */

	val = 0ULL;

	val = SET_FIELD(VAS_WINCTL_REJ_NO_CREDIT, val, winctx->rej_no_credit);

	val = SET_FIELD(VAS_WINCTL_PIN, val, winctx->pin_win);

	val = SET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val, winctx->tx_wcred_mode);

	val = SET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val, winctx->rx_wcred_mode);

	val = SET_FIELD(VAS_WINCTL_TX_WORD_MODE, val, winctx->tx_word_mode);

	val = SET_FIELD(VAS_WINCTL_RX_WORD_MODE, val, winctx->rx_word_mode);

	val = SET_FIELD(VAS_WINCTL_FAULT_WIN, val, winctx->fault_win);

	val = SET_FIELD(VAS_WINCTL_NX_WIN, val, winctx->nx_win);

	val = SET_FIELD(VAS_WINCTL_OPEN, val, 1);

	write_hvwc_reg(window, VREG(WINCTL), val);



	return 0;

}



/* stub for now */

int vas_win_close(struct vas_window *window)

{

arch/powerpc/platforms/powernv/vas.h

+55 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/atomic.h>

#include <linux/idr.h>

#include <asm/vas.h>

#include <linux/io.h>



/*

 * Overview of Virtual Accelerator Switchboard (VAS).
@@ -381,4 +382,58 @@ struct vas_winctx { 


extern struct vas_instance *find_vas_instance(int vasid);



/*

 * VREG(x):

 * Expand a register's short name (eg: LPID) into two parameters:

 *	- the register's short name in string form ("LPID"), and

 *	- the name of the macro (eg: VAS_LPID_OFFSET), defining the

 *	  register's offset in the window context

 */

#define VREG_SFX(n, s)	__stringify(n), VAS_##n##s

#define VREG(r)		VREG_SFX(r, _OFFSET)



#ifdef vas_debug

static inline void vas_log_write(struct vas_window *win, char *name,

			void *regptr, u64 val)

{

	if (val)

		pr_err("%swin #%d: %s reg %p, val 0x%016llx\n",

				win->tx_win ? "Tx" : "Rx", win->winid, name,

				regptr, val);

}



#else	/* vas_debug */



#define vas_log_write(win, name, reg, val)



#endif	/* vas_debug */



static inline void write_uwc_reg(struct vas_window *win, char *name,

			s32 reg, u64 val)

{

	void *regptr;



	regptr = win->uwc_map + reg;

	vas_log_write(win, name, regptr, val);



	out_be64(regptr, val);

}



static inline void write_hvwc_reg(struct vas_window *win, char *name,

			s32 reg, u64 val)

{

	void *regptr;



	regptr = win->hvwc_map + reg;

	vas_log_write(win, name, regptr, val);



	out_be64(regptr, val);

}



static inline u64 read_hvwc_reg(struct vas_window *win,

			char *name __maybe_unused, s32 reg)

{

	return in_be64(win->hvwc_map+reg);

}



#endif /* _VAS_H */