Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b15c9d35 authored by Gregory CLEMENT's avatar Gregory CLEMENT
Browse files

ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes 



This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K SoCs.

This follow the changes already made in the binding documentation (as
well as in the driver): "PCI: armada8k: Fix clock resource by adding
a register clock"

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent ef04faf1

arch/arm64/boot/dts/marvell/armada-cp110.dtsi

+6 −3
Original line number Diff line number Diff line
@@ -433,7 +433,8 @@ 
		interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <1>;

		clocks = <&CP110_LABEL(clk) 1 13>;

		clock-names = "core", "reg";

		clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;

		status = "disabled";

	};
@@ -460,7 +461,8 @@ 
		interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;



		num-lanes = <1>;

		clocks = <&CP110_LABEL(clk) 1 11>;

		clock-names = "core", "reg";

		clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;

		status = "disabled";

	};
@@ -487,7 +489,8 @@ 
		interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;



		num-lanes = <1>;

		clocks = <&CP110_LABEL(clk) 1 12>;

		clock-names = "core", "reg";

		clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;

		status = "disabled";

	};

};