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Commit b1314e3f authored by Radha Mohan Chintakuntla's avatar Radha Mohan Chintakuntla Committed by Tejun Heo
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ahci: Add support for Cavium's fifth generation SATA controller 



This patch adds support for Cavium's fifth generation SATA controller.
It is an on-chip controller and complies with AHCI 1.3.1. As the
controller uses 64-bit addresses it cannot use the standard AHCI BAR5
and so uses BAR4.

Signed-off-by: default avatarRadha Mohan Chintakuntla <rchintakuntla@cavium.com>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent 03b623fb

drivers/ata/ahci.c

+7 −2
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ enum { 
	AHCI_PCI_BAR_STA2X11	= 0,

	AHCI_PCI_BAR_CAVIUM	= 0,

	AHCI_PCI_BAR_ENMOTUS	= 2,

	AHCI_PCI_BAR_CAVIUM_GEN5	= 4,

	AHCI_PCI_BAR_STANDARD	= 5,

};
@@ -1567,8 +1568,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
		ahci_pci_bar = AHCI_PCI_BAR_STA2X11;

	else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)

		ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;

	else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)

	else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {

		if (pdev->device == 0xa01c)

			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;

		if (pdev->device == 0xa084)

			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;

	}



	/* acquire resources */

	rc = pcim_enable_device(pdev);