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Commit b0c1ef52 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86: Fix exclusion of BTS and LBR for Goldmont 



An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: <stable@vger.kernel.org>
Fixes: ccbebba4 ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 6de75a37

arch/x86/events/core.c

+6 −2
Original line number Original line Diff line number Diff line
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what) 
{

{

	int i;

	int i;





	if (x86_pmu.lbr_pt_coexist)

	/*

	 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.

	 * LBR and BTS are still mutually exclusive.

	 */

	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)

		return 0;

		return 0;





	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {

	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ int x86_add_exclusive(unsigned int what) 




void x86_del_exclusive(unsigned int what)

void x86_del_exclusive(unsigned int what)

{

{

	if (x86_pmu.lbr_pt_coexist)

	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)

		return;

		return;





	atomic_dec(&x86_pmu.lbr_exclusive[what]);

	atomic_dec(&x86_pmu.lbr_exclusive[what]);

arch/x86/events/perf_event.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -604,7 +604,7 @@ struct x86_pmu { 
	u64		lbr_sel_mask;		   /* LBR_SELECT valid bits */

	u64		lbr_sel_mask;		   /* LBR_SELECT valid bits */

	const int	*lbr_sel_map;		   /* lbr_select mappings */

	const int	*lbr_sel_map;		   /* lbr_select mappings */

	bool		lbr_double_abort;	   /* duplicated lbr aborts */

	bool		lbr_double_abort;	   /* duplicated lbr aborts */

	bool		lbr_pt_coexist;		   /* LBR may coexist with PT */

	bool		lbr_pt_coexist;		   /* (LBR|BTS) may coexist with PT */





	/*

	/*

	 * Intel PT/LBR/BTS are exclusive

	 * Intel PT/LBR/BTS are exclusive