Commit b095ae2b authored Feb 19, 2013 by Joseph Lo Committed by Stephen Warren Mar 11, 2013

ARM: tegra: don't unlock MMIO access to DBGLAR



There is no need to unlock MMIO access to the DBGLAR all the time. Doing
so may even cause problems if a SW bug causes writes to that MMIO region.

Cortex-A15 processors do not support the CP14 register write the code
currently uses to unlock the DBGLAR; the instruction throws an undefined
instruction exceptions. This prevents tegra_secondary_startup() from
executing on Tegra114, and hence prevents SMP.

Remove the code that unlocks this access.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

parent bf161d21

arch/arm/mach-tegra/headsmp.S

+0 −3

Original line number	Diff line number	Diff line
		@@ -7,8 +7,5 @@

		ENTRY(tegra_secondary_startup)
		bl v7_invalidate_l1
		/* Enable coresight */
		mov32 r0, 0xC5ACCE55
		mcr p14, 0, r0, c7, c12, 6
		b secondary_startup
		ENDPROC(tegra_secondary_startup)

arch/arm/mach-tegra/reset-handler.S

+0 −3

Original line number	Diff line number	Diff line
		@@ -41,9 +41,6 @@
		*/
		ENTRY(tegra_resume)
		bl v7_invalidate_l1
		/* Enable coresight */
		mov32 r0, 0xC5ACCE55
		mcr p14, 0, r0, c7, c12, 6

		cpu_id r0
		cmp r0, #0 @ CPU0?