Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit afdd8b61 authored by Murali Karicheri's avatar Murali Karicheri Committed by Santosh Shilimkar
Browse files

ARM: keystone: dts: fix typo in the ddr3 pllclk node name 



Fix following typo
 ddr3allclk -> ddr3apllclk
 ddr3bllclk -> ddr3bpllclk

Signed-off-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent b8273f2e

arch/arm/boot/dts/keystone-clocks.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ clocks { 
		reg-names = "control";

	};



	ddr3allclk: ddr3apllclk@2620360 {

	ddr3apllclk: ddr3apllclk@2620360 {

		#clock-cells = <0>;

		compatible = "ti,keystone,pll-clock";

		clocks = <&refclkddr3a>;
@@ -40,7 +40,7 @@ clocks { 
		reg-names = "control";

	};



	ddr3bllclk: ddr3bpllclk@2620368 {

	ddr3bpllclk: ddr3bpllclk@2620368 {

		#clock-cells = <0>;

		compatible = "ti,keystone,pll-clock";

		clocks = <&refclkddr3b>;