Commit afd58e79 authored Jan 22, 2014 by Ville Syrjälä Committed by Daniel Vetter Jan 29, 2014

drm/i915: Clarify WaDisable4x2SubspanOptimization situation for VLV



WaDisable4x2SubspanOptimization isn't listed for VLV in the workaround
database, but BSpec says that the relevant bit must be set. Add a
comment to remind people of this.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 46680e0a

drivers/gpu/drm/i915/intel_pm.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -4945,6 +4945,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)

		I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);

		/*
		* BSpec says this must be set, even though
		* WaDisable4x2SubspanOptimization isn't listed for VLV.
		*/
		I915_WRITE(CACHE_MODE_1,
		_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));