Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit af5a75a3 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv"" 



The performance regression from the CHV RC6 EI->TO change is now fixed
so re-enable TO mode for better RC6 resicency.

This reverts commit e85a5c79.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak <S&lt;deepak.s@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3cbdb48f

drivers/gpu/drm/i915/intel_pm.c

+3 −2
Original line number Diff line number Diff line
@@ -4724,7 +4724,8 @@ static void cherryview_enable_rps(struct drm_device *dev) 
		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);

	I915_WRITE(GEN6_RC_SLEEP, 0);



	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */

	/* TO threshold set to 1750 us ( 0x557 * 1.28 us) */

	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);



	/* allows RC6 residency counter to work */

	I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4738,7 +4739,7 @@ static void cherryview_enable_rps(struct drm_device *dev) 
	/* 3: Enable RC6 */

	if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&

						(pcbr >> VLV_PCBR_ADDR_SHIFT))

		rc6_mode = GEN6_RC_CTL_EI_MODE(1);

		rc6_mode = GEN7_RC_CTL_TO_MODE;



	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);