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Unverified Commit af4f7f38 authored by Nicolin Chen's avatar Nicolin Chen Committed by Mark Brown
Browse files

ASoC: fsl_ssi: Refine indentations and wrappings 



This patch just simply unifies the coding style.

Signed-off-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Tested-by: default avatarMaciej S. Szmigiero <mail@maciej.szmigiero.name>
Reviewed-by: default avatarMaciej S. Szmigiero <mail@maciej.szmigiero.name>
Acked-by: default avatarTimur Tabi <timur@tabi.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent a818aa5f

sound/soc/fsl/fsl_ssi.c

+115 −124
Original line number Diff line number Diff line
@@ -69,21 +69,35 @@ 
 * samples will be written to STX properly.

 */

#ifdef __BIG_ENDIAN

#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \

	 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \

	 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)

#define FSLSSI_I2S_FORMATS \

	(SNDRV_PCM_FMTBIT_S8 | \

	 SNDRV_PCM_FMTBIT_S16_BE | \

	 SNDRV_PCM_FMTBIT_S18_3BE | \

	 SNDRV_PCM_FMTBIT_S20_3BE | \

	 SNDRV_PCM_FMTBIT_S24_3BE | \

	 SNDRV_PCM_FMTBIT_S24_BE)

#else

#define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \

	 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \

	 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)

#define FSLSSI_I2S_FORMATS \

	(SNDRV_PCM_FMTBIT_S8 | \

	 SNDRV_PCM_FMTBIT_S16_LE | \

	 SNDRV_PCM_FMTBIT_S18_3LE | \

	 SNDRV_PCM_FMTBIT_S20_3LE | \

	 SNDRV_PCM_FMTBIT_S24_3LE | \

	 SNDRV_PCM_FMTBIT_S24_LE)

#endif



#define FSLSSI_SIER_DBG_RX_FLAGS (SSI_SIER_RFF0_EN | \

		SSI_SIER_RLS_EN | SSI_SIER_RFS_EN | \

		SSI_SIER_ROE0_EN | SSI_SIER_RFRC_EN)

#define FSLSSI_SIER_DBG_TX_FLAGS (SSI_SIER_TFE0_EN | \

		SSI_SIER_TLS_EN | SSI_SIER_TFS_EN | \

		SSI_SIER_TUE0_EN | SSI_SIER_TFRC_EN)

#define FSLSSI_SIER_DBG_RX_FLAGS \

	(SSI_SIER_RFF0_EN | \

	 SSI_SIER_RLS_EN | \

	 SSI_SIER_RFS_EN | \

	 SSI_SIER_ROE0_EN | \

	 SSI_SIER_RFRC_EN)

#define FSLSSI_SIER_DBG_TX_FLAGS \

	(SSI_SIER_TFE0_EN | \

	 SSI_SIER_TLS_EN | \

	 SSI_SIER_TFS_EN | \

	 SSI_SIER_TUE0_EN | \

	 SSI_SIER_TFRC_EN)



enum fsl_ssi_type {

	FSL_SSI_MCP8610,
@@ -442,8 +456,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, 


	regmap_read(regs, REG_SSI_SCR, &scr_val);



	nr_active_streams = !!(scr_val & SSI_SCR_TE) +

				!!(scr_val & SSI_SCR_RE);

	nr_active_streams = !!(scr_val & SSI_SCR_TE) + !!(scr_val & SSI_SCR_RE);



	if (nr_active_streams - 1 > 0)

		keep_active = 1;
@@ -474,8 +487,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, 
	 * 2) Disable all remaining bits of both streams when last stream ends

	 */

	if (ssi->soc->offline_config) {

		if ((enable && !nr_active_streams) ||

				(!enable && !keep_active))

		if ((enable && !nr_active_streams) || (!enable && !keep_active))

			fsl_ssi_rxtx_config(ssi, enable);



		goto config_done;
@@ -544,7 +556,6 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, 
	}

}





static void fsl_ssi_rx_config(struct fsl_ssi *ssi, bool enable)

{

	fsl_ssi_config(ssi, enable, &ssi->rxtx_reg_val.rx);
@@ -615,14 +626,11 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) 
	struct regmap *regs = ssi->regs;



	/* Setup the clock control register */

	regmap_write(regs, REG_SSI_STCCR,

			SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));

	regmap_write(regs, REG_SSI_SRCCR,

			SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));

	regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));

	regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));



	/* Enable AC97 mode and startup the SSI */

	regmap_write(regs, REG_SSI_SACNT,

			SSI_SACNT_AC97EN | SSI_SACNT_FV);

	regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);



	/* AC97 has to communicate with codec before starting a stream */

	regmap_update_bits(regs, REG_SSI_SCR,
@@ -663,7 +671,6 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 
	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);



	clk_disable_unprepare(ssi->clk);



}



/**
@@ -764,8 +771,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 


	stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |

		(psr ? SSI_SxCCR_PSR : 0);

	mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 |

		SSI_SxCCR_PSR;

	mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)

		regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr);
@@ -795,7 +801,8 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 
 *    fsl_ssi_set_bclk() if SSI is the DAI clock master.

 */

static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,

	struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)

			     struct snd_pcm_hw_params *hw_params,

			     struct snd_soc_dai *cpu_dai)

{

	struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);

	struct regmap *regs = ssi->regs;
@@ -837,8 +844,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 
		u8 i2smode;

		/* Normal + Network mode to send 16-bit data in 32-bit frames */

		if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)

			i2smode = SSI_SCR_I2S_MODE_NORMAL |

				SSI_SCR_NET;

			i2smode = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;

		else

			i2smode = ssi->i2s_mode;
@@ -850,11 +856,9 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 
	/* In synchronous mode, the SSI uses STCCR for capture */

	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||

	    ssi->cpu_dai_drv.symmetric_rates)

		regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK,

				wl);

		regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK, wl);

	else

		regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK,

				wl);

		regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK, wl);



	return 0;

}
@@ -896,8 +900,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, 
	scr |= SSI_SCR_SYNC_TX_FS;



	mask = SSI_STCR_TXBIT0 | SSI_STCR_TFDIR | SSI_STCR_TXDIR |

		SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL |

		SSI_STCR_TEFS;

	       SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL | SSI_STCR_TEFS;

	regmap_read(regs, REG_SSI_STCR, &stcr);

	regmap_read(regs, REG_SSI_SRCR, &srcr);

	stcr &= ~mask;
@@ -908,11 +911,9 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, 
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {

	case SND_SOC_DAIFMT_I2S:

		regmap_update_bits(regs, REG_SSI_STCCR,

				   SSI_SxCCR_DC_MASK,

				   SSI_SxCCR_DC(2));

				   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2));

		regmap_update_bits(regs, REG_SSI_SRCCR,

				   SSI_SxCCR_DC_MASK,

				   SSI_SxCCR_DC(2));

				   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2));

		switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {

		case SND_SOC_DAIFMT_CBM_CFS:

		case SND_SOC_DAIFMT_CBS_CFS:
@@ -940,8 +941,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, 
		break;

	case SND_SOC_DAIFMT_DSP_B:

		/* Data on rising edge of bclk, frame high */

		strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP |

			SSI_STCR_TXBIT0;

		strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TXBIT0;

		break;

	case SND_SOC_DAIFMT_AC97:

		/* Data on falling edge of bclk, frame high, 1clk before data */
@@ -1016,19 +1016,18 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, 
		     SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));



	if (ssi->use_dual_fifo) {

		regmap_update_bits(regs, REG_SSI_SRCR, SSI_SRCR_RFEN1,

				SSI_SRCR_RFEN1);

		regmap_update_bits(regs, REG_SSI_STCR, SSI_STCR_TFEN1,

				SSI_STCR_TFEN1);

		regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_TCH_EN,

				SSI_SCR_TCH_EN);

		regmap_update_bits(regs, REG_SSI_SRCR,

				   SSI_SRCR_RFEN1, SSI_SRCR_RFEN1);

		regmap_update_bits(regs, REG_SSI_STCR,

				   SSI_STCR_TFEN1, SSI_STCR_TFEN1);

		regmap_update_bits(regs, REG_SSI_SCR,

				   SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);

	}



	if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)

		fsl_ssi_setup_ac97(ssi);



	return 0;



}



/**
@@ -1069,17 +1068,16 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 
		return -EINVAL;

	}



	regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_DC_MASK,

			SSI_SxCCR_DC(slots));

	regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_DC_MASK,

			SSI_SxCCR_DC(slots));

	regmap_update_bits(regs, REG_SSI_STCCR,

			   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));

	regmap_update_bits(regs, REG_SSI_SRCCR,

			   SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));



	/* Save SSIEN bit of the SCR register */

	regmap_read(regs, REG_SSI_SCR, &val);

	val &= SSI_SCR_SSIEN;

	/* Temporarily enable SSI to allow SxMSKs to be configurable */

	regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN,

			SSI_SCR_SSIEN);

	regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);



	regmap_write(regs, REG_SSI_STMSK, ~tx_mask);

	regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
@@ -1206,7 +1204,6 @@ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 
	.ops = &fsl_ssi_dai_ops,

};





static struct fsl_ssi *fsl_ac97_data;



static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
@@ -1235,8 +1232,8 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 
	lval = val << 4;

	regmap_write(regs, REG_SSI_SACDAT, lval);



	regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK,

			SSI_SACNT_WR);

	regmap_update_bits(regs, REG_SSI_SACNT,

			   SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);

	udelay(100);



	clk_disable_unprepare(fsl_ac97_data->clk);
@@ -1249,7 +1246,6 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 
					unsigned short reg)

{

	struct regmap *regs = fsl_ac97_data->regs;



	unsigned short val = 0;

	u32 reg_val;

	unsigned int lreg;
@@ -1259,15 +1255,14 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 


	ret = clk_prepare_enable(fsl_ac97_data->clk);

	if (ret) {

		pr_err("ac97 read clk_prepare_enable failed: %d\n",

			ret);

		pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);

		goto ret_unlock;

	}



	lreg = (reg & 0x7f) <<  12;

	regmap_write(regs, REG_SSI_SACADD, lreg);

	regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK,

			SSI_SACNT_RD);

	regmap_update_bits(regs, REG_SSI_SACNT,

			   SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);



	udelay(100);
@@ -1370,14 +1365,13 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, 
	return 0;



error_pcm:



	if (!ssi->has_ipg_clk_name)

		clk_disable_unprepare(ssi->clk);



	return ret;

}



static void fsl_ssi_imx_clean(struct platform_device *pdev,

		struct fsl_ssi *ssi)

static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)

{

	if (!ssi->use_dma)

		imx_pcm_fiq_exit(pdev);
@@ -1423,7 +1417,6 @@ static int fsl_ssi_probe(struct platform_device *pdev) 
	if (fsl_ssi_is_ac97(ssi)) {

		memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,

		       sizeof(fsl_ssi_ac97_dai));



		fsl_ac97_data = ssi;

	} else {

		memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
@@ -1582,8 +1575,8 @@ static int fsl_ssi_probe(struct platform_device *pdev) 
			goto error_sound_card;

		}



		ssi->pdev = platform_device_register_data(NULL,

					"ac97-codec", ssi_idx, NULL, 0);

		ssi->pdev = platform_device_register_data(NULL, "ac97-codec",

							  ssi_idx, NULL, 0);

		if (IS_ERR(ssi->pdev)) {

			ret = PTR_ERR(ssi->pdev);

			dev_err(dev,
@@ -1597,11 +1590,9 @@ static int fsl_ssi_probe(struct platform_device *pdev) 


error_sound_card:

	fsl_ssi_debugfs_remove(&ssi->dbg_stats);



error_asoc_register:

	if (fsl_ssi_is_ac97(ssi))

		snd_soc_set_ac97_ops(NULL);



error_ac97_ops:

	if (fsl_ssi_is_ac97(ssi))

		mutex_destroy(&ssi->ac97_reg_lock);

sound/soc/fsl/fsl_ssi_dbg.c

+2 −1
Original line number Diff line number Diff line
@@ -147,7 +147,8 @@ int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev) 
		return -ENOMEM;



	ssi_dbg->dbg_stats = debugfs_create_file("stats", S_IRUGO,

			ssi_dbg->dbg_dir, ssi_dbg, &fsl_ssi_stats_ops);

						 ssi_dbg->dbg_dir, ssi_dbg,

						 &fsl_ssi_stats_ops);

	if (!ssi_dbg->dbg_stats) {

		debugfs_remove(ssi_dbg->dbg_dir);

		return -ENOMEM;

sound/soc/fsl/fsl_ssi.h

+1 −1

File changed.

Contains only whitespace changes.