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Commit af2418be authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle
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MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value 



Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: default avatarDaniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
parent a4c0201e

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ config BCM63XX 
	select SWAP_IO_SPACE

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_CLK

	select MIPS_L1_CACHE_SHIFT_4

	help

	 Support for BCM63XX based boards