Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit af040ffc authored by Russell King's avatar Russell King
Browse files

ARM: make it easier to check the CPU part number correctly 



Ensure that platform maintainers check the CPU part number in the right
manner: the CPU part number is meaningless without also checking the
CPU implement(e|o)r (choose your preferred spelling!)  Provide an
interface which returns both the implementer and part number together,
and update the definitions to include the implementer.

Mark the old function as being deprecated... indeed, using the old
function with the definitions will now always evaluate as false, so
people must update their un-merged code to the new function.  While
this could be avoided by adding new definitions, we'd also have to
create new names for them which would be awkward.

Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent ee2593ef

arch/arm/include/asm/cputype.h

+24 −13
Original line number Diff line number Diff line
@@ -62,17 +62,18 @@ 
#define ARM_CPU_IMP_ARM			0x41

#define ARM_CPU_IMP_INTEL		0x69



#define ARM_CPU_PART_ARM1136		0xB360

#define ARM_CPU_PART_ARM1156		0xB560

#define ARM_CPU_PART_ARM1176		0xB760

#define ARM_CPU_PART_ARM11MPCORE	0xB020

#define ARM_CPU_PART_CORTEX_A8		0xC080

#define ARM_CPU_PART_CORTEX_A9		0xC090

#define ARM_CPU_PART_CORTEX_A5		0xC050

#define ARM_CPU_PART_CORTEX_A15		0xC0F0

#define ARM_CPU_PART_CORTEX_A7		0xC070

#define ARM_CPU_PART_CORTEX_A12		0xC0D0

#define ARM_CPU_PART_CORTEX_A17		0xC0E0

/* ARM implemented processors */

#define ARM_CPU_PART_ARM1136		0x4100b360

#define ARM_CPU_PART_ARM1156		0x4100b560

#define ARM_CPU_PART_ARM1176		0x4100b760

#define ARM_CPU_PART_ARM11MPCORE	0x4100b020

#define ARM_CPU_PART_CORTEX_A8		0x4100c080

#define ARM_CPU_PART_CORTEX_A9		0x4100c090

#define ARM_CPU_PART_CORTEX_A5		0x4100c050

#define ARM_CPU_PART_CORTEX_A7		0x4100c070

#define ARM_CPU_PART_CORTEX_A12		0x4100c0d0

#define ARM_CPU_PART_CORTEX_A17		0x4100c0e0

#define ARM_CPU_PART_CORTEX_A15		0x4100c0f0



#define ARM_CPU_XSCALE_ARCH_MASK	0xe000

#define ARM_CPU_XSCALE_ARCH_V1		0x2000
@@ -171,14 +172,24 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 
	return (read_cpuid_id() & 0xFF000000) >> 24;

}



static inline unsigned int __attribute_const__ read_cpuid_part_number(void)

/*

 * The CPU part number is meaningless without referring to the CPU

 * implementer: implementers are free to define their own part numbers

 * which are permitted to clash with other implementer part numbers.

 */

static inline unsigned int __attribute_const__ read_cpuid_part(void)

{

	return read_cpuid_id() & 0xff00fff0;

}



static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)

{

	return read_cpuid_id() & 0xFFF0;

}



static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)

{

	return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;

	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;

}



static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)

arch/arm/include/asm/smp_scu.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 


static inline bool scu_a9_has_base(void)

{

	return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;

	return read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;

}



static inline unsigned long scu_a9_get_base(void)

arch/arm/kernel/perf_event_cpu.c

+27 −28
Original line number Diff line number Diff line
@@ -250,15 +250,12 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = { 
static int probe_current_pmu(struct arm_pmu *pmu)

{

	int cpu = get_cpu();

	unsigned long implementor = read_cpuid_implementor();

	unsigned long part_number = read_cpuid_part_number();

	int ret = -ENODEV;



	pr_info("probing PMU on CPU %d\n", cpu);



	switch (read_cpuid_part()) {

	/* ARM Ltd CPUs. */

	if (implementor == ARM_CPU_IMP_ARM) {

		switch (part_number) {

	case ARM_CPU_PART_ARM1136:

	case ARM_CPU_PART_ARM1156:

	case ARM_CPU_PART_ARM1176:
@@ -273,9 +270,9 @@ static int probe_current_pmu(struct arm_pmu *pmu) 
	case ARM_CPU_PART_CORTEX_A9:

		ret = armv7_a9_pmu_init(pmu);

		break;

		}

	/* Intel CPUs [xscale]. */

	} else if (implementor == ARM_CPU_IMP_INTEL) {



	default:

		if (read_cpuid_implementor() == ARM_CPU_IMP_INTEL) {

			switch (xscale_cpu_arch_version()) {

			case ARM_CPU_XSCALE_ARCH_V1:

				ret = xscale1pmu_init(pmu);
@@ -285,6 +282,8 @@ static int probe_current_pmu(struct arm_pmu *pmu) 
				break;

			}

		}

		break;

	}



	put_cpu();

	return ret;

arch/arm/kvm/guest.c

+1 −7
Original line number Diff line number Diff line
@@ -274,13 +274,7 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 


int __attribute_const__ kvm_target_cpu(void)

{

	unsigned long implementor = read_cpuid_implementor();

	unsigned long part_number = read_cpuid_part_number();



	if (implementor != ARM_CPU_IMP_ARM)

		return -EINVAL;



	switch (part_number) {

	switch (read_cpuid_part()) {

	case ARM_CPU_PART_CORTEX_A7:

		return KVM_ARM_TARGET_CORTEX_A7;

	case ARM_CPU_PART_CORTEX_A15:

arch/arm/mach-exynos/mcpm-exynos.c

+2 −2
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ static void exynos_power_down(void) 
	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {

		arch_spin_unlock(&exynos_mcpm_lock);



		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {

		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {

			/*

			 * On the Cortex-A15 we need to disable

			 * L2 prefetching before flushing the cache.
@@ -291,7 +291,7 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level) 


static void __init exynos_cache_off(void)

{

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {

		/* disable L2 prefetching on the Cortex-A15 */

		asm volatile(

		"mcr	p15, 1, %0, c15, c0, 3\n\t"