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Commit ae75d908 authored by Will Deacon's avatar Will Deacon Committed by Ingo Molnar
Browse files

locking/qspinlock: Use try_cmpxchg() instead of cmpxchg() when locking 



When reaching the head of an uncontended queue on the qspinlock slow-path,
using a try_cmpxchg() instead of a cmpxchg() operation to transition the
lock work to _Q_LOCKED_VAL generates slightly better code for x86 and
pretty much identical code for arm64.

Reported-by: default avatarPeter Zijlstra <peterz@infradead.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarWaiman Long <longman@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: boqun.feng@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1524738868-31318-13-git-send-email-will.deacon@arm.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 9d4646d1

kernel/locking/qspinlock.c

+9 −10
Original line number Diff line number Diff line
@@ -467,16 +467,15 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) 
	 * Otherwise, we only need to grab the lock.

	 */



	/* In the PV case we might already have _Q_LOCKED_VAL set */

	if ((val & _Q_TAIL_MASK) == tail) {

	/*

	 * In the PV case we might already have _Q_LOCKED_VAL set.

	 *

	 * The atomic_cond_read_acquire() call above has provided the

	 * necessary acquire semantics required for locking.

	 */

		old = atomic_cmpxchg_relaxed(&lock->val, val, _Q_LOCKED_VAL);

		if (old == val)

	if (((val & _Q_TAIL_MASK) == tail) &&

	    atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL))

		goto release; /* No contention */

	}



	/* Either somebody is queued behind us or _Q_PENDING_VAL is set */

	set_locked(lock);