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Commit ae3fabcd authored by Mike Leach's avatar Mike Leach Committed by Greg Kroah-Hartman
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coresight: etm4x: Fix enabling of cycle accurate tracing in perf. 



Using perf record 'cyclacc' option in cs_etm event was not setting up cycle
accurate trace correctly.

Corrects bit set in TRCCONFIGR to enable cycle accurate trace.
Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec.

Signed-off-by: default avatarMike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f0944463

drivers/hwtracing/coresight/coresight-etm4x.c

+5 −2
Original line number Diff line number Diff line
@@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, 
		goto out;



	/* Go from generic option to ETMv4 specifics */

	if (attr->config & BIT(ETM_OPT_CYCACC))

		config->cfg |= ETMv4_MODE_CYCACC;

	if (attr->config & BIT(ETM_OPT_CYCACC)) {

		config->cfg |= BIT(4);

		/* TRM: Must program this for cycacc to work */

		config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;

	}

	if (attr->config & BIT(ETM_OPT_TS))

		config->cfg |= ETMv4_MODE_TIMESTAMP;

drivers/hwtracing/coresight/coresight-etm4x.h

+1 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ 
#define ETM_ARCH_V4			0x40

#define ETMv4_SYNC_MASK			0x1F

#define ETM_CYC_THRESHOLD_MASK		0xFFF

#define ETM_CYC_THRESHOLD_DEFAULT       0x100

#define ETMv4_EVENT_MASK		0xFF

#define ETM_CNTR_MAX_VAL		0xFFFF

#define ETM_TRACEID_MASK		0x3f