Merge tag 'marvell-mvebu-clk-3.8' of...

- compatible: Should be "marvell,armada-370-xp-timer"

- compatible: Should be "marvell,armada-370-xp-timer"

- interrupts: Should contain the list of Global Timer interrupts

- interrupts: Should contain the list of Global Timer interrupts

- reg: Should contain the base address of the Global Timer registers

- reg: Should contain the base address of the Global Timer registers

- clocks: clock driving the timer hardware

Optional properties:

Optional properties:

- marvell,timer-25Mhz: Tells whether the Global timer supports the 25

- marvell,timer-25Mhz: Tells whether the Global timer supports the 25

* Core Clock bindings for Marvell MVEBU SoCs

Marvell MVEBU SoCs usually allow to determine core clock frequencies by

reading the Sample-At-Reset (SAR) register. The core clock consumer should

specify the desired clock by having the clock ID in its "clocks" phandle cell.

The following is a list of provided IDs and clock names on Armada 370/XP:

 0 = tclk    (Internal Bus clock)

 1 = cpuclk  (CPU clock)

 2 = nbclk   (L2 Cache clock)

 3 = hclk    (DRAM control clock)

 4 = dramclk (DDR clock)

The following is a list of provided IDs and clock names on Kirkwood and Dove:

 0 = tclk   (Internal Bus clock)

 1 = cpuclk (CPU0 clock)

 2 = l2clk  (L2 Cache clock derived from CPU0 clock)

 3 = ddrclk (DDR controller clock derived from CPU0 clock)

Required properties:

- compatible : shall be one of the following:

	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks

	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks

	"marvell,dove-core-clock" - for Dove SoC core clocks

	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)

	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC

- reg : shall be the register address of the Sample-At-Reset (SAR) register

- #clock-cells : from common clock binding; shall be set to 1

Optional properties:

- clock-output-names : from common clock binding; allows overwrite default clock

	output names ("tclk", "cpuclk", "l2clk", "ddrclk")

Example:

core_clk: core-clocks@d0214 {

	compatible = "marvell,dove-core-clock";

	reg = <0xd0214 0x4>;

	#clock-cells = <1>;

};

spi0: spi@10600 {

	compatible = "marvell,orion-spi";

	/* ... */

	/* get tclk from core clock provider */

	clocks = <&core_clk 0>;

};

Device Tree Clock bindings for cpu clock of Marvell EBU platforms

Required properties:

- compatible : shall be one of the following:

	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP

- reg : Address and length of the clock complex register set

- #clock-cells : should be set to 1.

- clocks : shall be the input parent clock phandle for the clock.

cpuclk: clock-complex@d0018700 {

	#clock-cells = <1>;

	compatible = "marvell,armada-xp-cpu-clock";

	reg = <0xd0018700 0xA0>;

	clocks = <&coreclk 1>;

}

cpu@0 {

	compatible = "marvell,sheeva-v7";

	reg = <0>;

	clocks = <&cpuclk 0>;

};

* Gated Clock bindings for Marvell Orion SoCs

Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save

some power. The clock consumer should specify the desired clock by having

the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to

the corresponding clock gating control bit in HW to ease manual clock lookup

in datasheet.

The following is a list of provided IDs for Armada 370:

ID	Clock	Peripheral

-----------------------------------

0	Audio	AC97 Cntrl

1	pex0_en	PCIe 0 Clock out

2	pex1_en	PCIe 1 Clock out

3	ge1	Gigabit Ethernet 1

4	ge0	Gigabit Ethernet 0

5	pex0	PCIe Cntrl 0

9	pex1	PCIe Cntrl 1

15	sata0	SATA Host 0

17	sdio	SDHCI Host

25	tdm	Time Division Mplx

28	ddr	DDR Cntrl

30	sata1	SATA Host 0

The following is a list of provided IDs for Armada XP:

ID	Clock	Peripheral

-----------------------------------

0	audio	Audio Cntrl

1	ge3	Gigabit Ethernet 3

2	ge2	Gigabit Ethernet 2

3	ge1	Gigabit Ethernet 1

4	ge0	Gigabit Ethernet 0

5	pex0	PCIe Cntrl 0

6	pex1	PCIe Cntrl 1

7	pex2	PCIe Cntrl 2

8	pex3	PCIe Cntrl 3

13	bp

14	sata0lnk

15	sata0	SATA Host 0

16	lcd	LCD Cntrl

17	sdio	SDHCI Host

18	usb0	USB Host 0

19	usb1	USB Host 1

20	usb2	USB Host 2

22	xor0	XOR DMA 0

23	crypto	CESA engine

25	tdm	Time Division Mplx

28	xor1	XOR DMA 1

29	sata1lnk

30	sata1	SATA Host 0

The following is a list of provided IDs for Dove:

ID	Clock	Peripheral

-----------------------------------

0	usb0	USB Host 0

1	usb1	USB Host 1

2	ge	Gigabit Ethernet

3	sata	SATA Host

4	pex0	PCIe Cntrl 0

5	pex1	PCIe Cntrl 1

8	sdio0	SDHCI Host 0

9	sdio1	SDHCI Host 1

10	nand	NAND Cntrl

11	camera	Camera Cntrl

12	i2s0	I2S Cntrl 0

13	i2s1	I2S Cntrl 1

15	crypto	CESA engine

21	ac97	AC97 Cntrl

22	pdma	Peripheral DMA

23	xor0	XOR DMA 0

24	xor1	XOR DMA 1

30	gephy	Gigabit Ethernel PHY

Note: gephy(30) is implemented as a parent clock of ge(2)

The following is a list of provided IDs for Kirkwood:

ID	Clock	Peripheral

-----------------------------------

0	ge0	Gigabit Ethernet 0

2	pex0	PCIe Cntrl 0

3	usb0	USB Host 0

4	sdio	SDIO Cntrl

5	tsu	Transp. Stream Unit

6	dunit	SDRAM Cntrl

7	runit	Runit

8	xor0	XOR DMA 0

9	audio	I2S Cntrl 0

14	sata0	SATA Host 0

15	sata1	SATA Host 1

16	xor1	XOR DMA 1

17	crypto	CESA engine

18	pex1	PCIe Cntrl 1

19	ge1	Gigabit Ethernet 0

20	tdm	Time Division Mplx

Required properties:

- compatible : shall be one of the following:

	"marvell,dove-gating-clock" - for Dove SoC clock gating

	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating

- reg : shall be the register address of the Clock Gating Control register

- #clock-cells : from common clock binding; shall be set to 1

Optional properties:

- clocks : default parent clock phandle (e.g. tclk)

Example:

gate_clk: clock-gating-control@d0038 {

	compatible = "marvell,dove-gating-clock";

	reg = <0xd0038 0x4>;

	/* default parent clock is tclk */

	clocks = <&core_clk 0>;

	#clock-cells = <1>;

};

sdio0: sdio@92000 {

	compatible = "marvell,dove-sdhci";

	/* get clk gate bit 8 (sdio0) */

	clocks = <&gate_clk 8>;

};

config ARCH_DOVE

config ARCH_DOVE

	bool "Marvell Dove"

	bool "Marvell Dove"

	select ARCH_REQUIRE_GPIOLIB

	select ARCH_REQUIRE_GPIOLIB

	select COMMON_CLK_DOVE

	select CPU_V7

	select CPU_V7

	select GENERIC_CLOCKEVENTS

	select GENERIC_CLOCKEVENTS

	select MIGHT_HAVE_PCI

	select MIGHT_HAVE_PCI