Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ad1f5caf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm 

Pull ARM fixes from Russell King:
 "A number of small fixes:
   - fix loading of the translation table base registers for LPAE
   - add two new syscalls to the ARM syscall tables"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: wire up memfd_create syscall
  ARM: wire up getrandom syscall
  ARM: 8114/1: LPAE: load upper bits of early TTBR0/TTBR1
parents e853ccf0 e57e4193

arch/arm/include/asm/unistd.h

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
 * This may need to be greater than __NR_last_syscall+1 in order to

 * account for the padding in the syscall table

 */

#define __NR_syscalls  (384)

#define __NR_syscalls  (388)



/*

 * *NOTE*: This is a ghost syscall private to the kernel.  Only the

arch/arm/include/uapi/asm/unistd.h

+2 −0
Original line number Diff line number Diff line
@@ -410,6 +410,8 @@ 
#define __NR_sched_getattr		(__NR_SYSCALL_BASE+381)

#define __NR_renameat2			(__NR_SYSCALL_BASE+382)

#define __NR_seccomp			(__NR_SYSCALL_BASE+383)

#define __NR_getrandom			(__NR_SYSCALL_BASE+384)

#define __NR_memfd_create		(__NR_SYSCALL_BASE+385)



/*

 * The following SWIs are ARM private.

arch/arm/kernel/calls.S

+2 −0
Original line number Diff line number Diff line
@@ -393,6 +393,8 @@ 
		CALL(sys_sched_getattr)

		CALL(sys_renameat2)

		CALL(sys_seccomp)

		CALL(sys_getrandom)

/* 385 */	CALL(sys_memfd_create)

#ifndef syscalls_counted

.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls

#define syscalls_counted

arch/arm/mm/proc-v7-3level.S

+3 −4
Original line number Diff line number Diff line
@@ -146,12 +146,11 @@ ENDPROC(cpu_v7_set_pte_ext) 
	mov	\tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits

	mov	\ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT		@ lower bits

	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET

	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1

	adcls	\tmp, \tmp, #0

	mcrr	p15, 1, \ttbr1, \tmp, c2			@ load TTBR1

	mov	\tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)	@ upper bits

	mov	\ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT		@ lower bits

	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0

	mcrr	p15, 1, \ttbr1, \zero, c2			@ load TTBR1

	mcrr	p15, 0, \ttbr0, \zero, c2			@ load TTBR0

	mcrr	p15, 0, \ttbr0, \tmp, c2			@ load TTBR0

	.endm



	/*