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Commit ad1c974b authored by Chris Zhong's avatar Chris Zhong Committed by Sean Paul
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drm/rockchip/dsi: fix insufficient bandwidth of some panel 



Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.

Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-7-git-send-email-zyw@rock-chips.com
parent 7df1207f

drivers/gpu/drm/rockchip/dw-mipi-dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -529,8 +529,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, 


	mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);

	if (mpclk) {

		/* take 1 / 0.9, since mbps must big than bandwidth of RGB */

		tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;

		/* take 1 / 0.8, since mbps must big than bandwidth of RGB */

		tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;

		if (tmp < max_mbps)

			target_mbps = tmp;

		else