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Commit aceae1bf authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: add smc msg for NB P-State switch 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarDavid Rokhvarg <David.Rokhvarg@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
parent 73c9f222

drivers/gpu/drm/amd/powerplay/inc/cz_ppsmc.h

+1 −0
Original line number Diff line number Diff line
@@ -164,6 +164,7 @@ enum DPM_ARRAY { 
#define PPSMC_MSG_SetLoggerAddressHigh        ((uint16_t) 0x26C)

#define PPSMC_MSG_SetLoggerAddressLow         ((uint16_t) 0x26D)

#define PPSMC_MSG_SetWatermarkFrequency       ((uint16_t) 0x26E)

#define PPSMC_MSG_SetDisplaySizePowerParams   ((uint16_t) 0x26F)



/* REMOVE LATER*/

#define PPSMC_MSG_DPM_ForceState              ((uint16_t) 0x104)

drivers/gpu/drm/amd/powerplay/inc/smu8_fusion.h

+8 −0
Original line number Diff line number Diff line
@@ -48,6 +48,14 @@ struct SMU8_Port80MonitorTable { 
	uint8_t  EnableDramShadow;

};



/*  Display specific power management parameters */

#define PWRMGT_SEPARATION_TIME_SHIFT            0

#define PWRMGT_SEPARATION_TIME_MASK             0xFFFF

#define PWRMGT_DISABLE_CPU_CSTATES_SHIFT        16

#define PWRMGT_DISABLE_CPU_CSTATES_MASK         0x1

#define PWRMGT_DISABLE_CPU_PSTATES_SHIFT        24

#define PWRMGT_DISABLE_CPU_PSTATES_MASK         0x1



/* Clock Table Definitions */

#define NUM_SCLK_LEVELS     8

#define NUM_LCLK_LEVELS     8