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Commit abf9c25d authored by Kefeng Wang's avatar Kefeng Wang Committed by Wei Xu
Browse files

arm64: dts: hip05: Append all gicv3 ITS entries 



There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.

Signed-off-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 6897db62

arch/arm64/boot/dts/hisilicon/hip05.dtsi

+19 −1
Original line number Diff line number Diff line
@@ -246,11 +246,29 @@ 
		      <0x0 0xfe020000 0 0x10000>;       /* GICV */

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



		its_totems: interrupt-controller@8c000000 {

		its_peri: interrupt-controller@8c000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			reg = <0x0 0x8c000000 0x0 0x40000>;

		};



		its_m3: interrupt-controller@a3000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			reg = <0x0 0xa3000000 0x0 0x40000>;

		};



		its_pcie: interrupt-controller@b7000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			reg = <0x0 0xb7000000 0x0 0x40000>;

		};



		its_dsa: interrupt-controller@c6000000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			reg = <0x0 0xc6000000 0x0 0x40000>;

		};

	};



	timer {