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Commit ab5c3b6b authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-fixes-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes 

From Shawn Guo, imx fixes for 3.12:

* A couple of clock driver and device tree fixes
* A bug fix for clk-fixup-mux to get imx6sl back to boot
* A L2 cache setting fix for imx6q
* One pinctrl macro fix for UART2 DTE entries

* tag 'imx-fixes-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6

:
  ARM: dts: imx6q: fix the wrong offset of the Pad Mux register
  ARM: imx: i.mx6d/q: disable the double linefill feature of PL310
  ARM: imx51.dtsi: fix PATA device clock
  ARM: mach-imx: clk-imx51-imx53: Fix 'spdif1_pred' clock registration
  ARM: imx: initialize clk_init_data.flags for clk-fixup-mux
  ARM: imx27.dtsi: fix CSPI PER clock id

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ab5be588 538bcbe2

arch/arm/boot/dts/imx27.dtsi

+3 −3
Original line number Original line Diff line number Diff line
@@ -187,7 +187,7 @@ 
				compatible = "fsl,imx27-cspi";

				compatible = "fsl,imx27-cspi";

				reg = <0x1000e000 0x1000>;

				reg = <0x1000e000 0x1000>;

				interrupts = <16>;

				interrupts = <16>;

				clocks = <&clks 53>, <&clks 53>;

				clocks = <&clks 53>, <&clks 60>;

				clock-names = "ipg", "per";

				clock-names = "ipg", "per";

				status = "disabled";

				status = "disabled";

			};

			};
@@ -198,7 +198,7 @@ 
				compatible = "fsl,imx27-cspi";

				compatible = "fsl,imx27-cspi";

				reg = <0x1000f000 0x1000>;

				reg = <0x1000f000 0x1000>;

				interrupts = <15>;

				interrupts = <15>;

				clocks = <&clks 52>, <&clks 52>;

				clocks = <&clks 52>, <&clks 60>;

				clock-names = "ipg", "per";

				clock-names = "ipg", "per";

				status = "disabled";

				status = "disabled";

			};

			};
@@ -309,7 +309,7 @@ 
				compatible = "fsl,imx27-cspi";

				compatible = "fsl,imx27-cspi";

				reg = <0x10017000 0x1000>;

				reg = <0x10017000 0x1000>;

				interrupts = <6>;

				interrupts = <6>;

				clocks = <&clks 51>, <&clks 51>;

				clocks = <&clks 51>, <&clks 60>;

				clock-names = "ipg", "per";

				clock-names = "ipg", "per";

				status = "disabled";

				status = "disabled";

			};

			};

arch/arm/boot/dts/imx51.dtsi

+1 −1
Original line number Original line Diff line number Diff line
@@ -474,7 +474,7 @@ 
				compatible = "fsl,imx51-pata", "fsl,imx27-pata";

				compatible = "fsl,imx51-pata", "fsl,imx27-pata";

				reg = <0x83fe0000 0x4000>;

				reg = <0x83fe0000 0x4000>;

				interrupts = <70>;

				interrupts = <70>;

				clocks = <&clks 161>;

				clocks = <&clks 172>;

				status = "disabled";

				status = "disabled";

			};

			};

arch/arm/boot/dts/imx6q-pinfunc.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -207,8 +207,8 @@ 
#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1

#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1

#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1

#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1

#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0

#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0

#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x0c4 0x3dc 0x000 0x4 0x0

#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x0c8 0x3dc 0x000 0x4 0x0

#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x0c4 0x3dc 0x924 0x4 0x1

#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x0c8 0x3dc 0x924 0x4 0x1

#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0

#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0

#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0

#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0

#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0

#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0

arch/arm/mach-imx/clk-fixup-mux.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -90,6 +90,7 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 
	init.ops = &clk_fixup_mux_ops;

	init.ops = &clk_fixup_mux_ops;

	init.parent_names = parents;

	init.parent_names = parents;

	init.num_parents = num_parents;

	init.num_parents = num_parents;

	init.flags = 0;





	fixup_mux->mux.reg = reg;

	fixup_mux->mux.reg = reg;

	fixup_mux->mux.shift = shift;

	fixup_mux->mux.shift = shift;

arch/arm/mach-imx/clk-imx51-imx53.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -397,7 +397,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 
				mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));

				mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));

	clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,

	clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,

				spdif_sel, ARRAY_SIZE(spdif_sel));

				spdif_sel, ARRAY_SIZE(spdif_sel));

	clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);

	clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);

	clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);

	clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);

	clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,

	clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,

				mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));

				mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));