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Commit ab57c2b4 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-soc-4.12' of... 

Merge tag 'imx-soc-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

i.MX SoC changes for 4.12:
 - A correction on mmdc_pmu_write_accesses event definition.
 - Add new axi_id perf command to support MMDC filter memory usage
   profiling.
 - Set correct SPI chip_select in platform device registration, so that
   spi-imx driver code can be improved to use chip_select directly for
   harwdare setup instead of indirectly via the cs_gpio mapping array.
 - Disable APIS bus supervisor protect for i.MX25, since the default
   configuration doesn't work for a few peripherals accessed through
   SDMA.
 - Add compatible check for the secondary generation of I2SE i.MX28
   Duckbill board support.

* tag 'imx-soc-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  ARM: mxs: add support for I2SE Duckbill 2 boards
  ARM: i.MX25: globally disable supervisor protect
  ARM: imx: set correct chip_select in platform setup
  ARM: imx: Add AXI address filter support for MMDC profiling
  ARM: imx: Fix mmdc_pmu_write_accesses event definition

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e7d2b857 ff8abc28

arch/arm/mach-imx/mach-imx25.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -23,6 +23,11 @@ static void __init imx25_init_early(void) 
	mxc_set_cpu_type(MXC_CPU_MX25);

	mxc_set_cpu_type(MXC_CPU_MX25);

}

}





static void __init imx25_dt_init(void)

{

	imx_aips_allow_unprivileged_access("fsl,imx25-aips");

}



static void __init mx25_init_irq(void)

static void __init mx25_init_irq(void)

{

{

	struct device_node *np;

	struct device_node *np;
@@ -41,6 +46,7 @@ static const char * const imx25_dt_board_compat[] __initconst = { 




DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")

DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")

	.init_early	= imx25_init_early,

	.init_early	= imx25_init_early,

	.init_machine	= imx25_dt_init,

	.init_late      = imx25_pm_init,

	.init_late      = imx25_pm_init,

	.init_irq	= mx25_init_irq,

	.init_irq	= mx25_init_irq,

	.dt_compat	= imx25_dt_board_compat,

	.dt_compat	= imx25_dt_board_compat,

arch/arm/mach-imx/mach-mx31_3ds.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -375,6 +375,8 @@ static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = { 




/* SPI */

/* SPI */

static int spi0_internal_chipselect[] = {

static int spi0_internal_chipselect[] = {

	MXC_SPI_CS(0),

	MXC_SPI_CS(1),

	MXC_SPI_CS(2),

	MXC_SPI_CS(2),

};

};
@@ -385,6 +387,7 @@ static const struct spi_imx_master spi0_pdata __initconst = { 




static int spi1_internal_chipselect[] = {

static int spi1_internal_chipselect[] = {

	MXC_SPI_CS(0),

	MXC_SPI_CS(0),

	MXC_SPI_CS(1),

	MXC_SPI_CS(2),

	MXC_SPI_CS(2),

};

};
@@ -398,7 +401,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { 
		.modalias	= "mc13783",

		.modalias	= "mc13783",

		.max_speed_hz	= 1000000,

		.max_speed_hz	= 1000000,

		.bus_num	= 1,

		.bus_num	= 1,

		.chip_select	= 1, /* SS2 */

		.chip_select	= 2, /* SS2 */

		.platform_data	= &mc13783_pdata,

		.platform_data	= &mc13783_pdata,

		/* irq number is run-time assigned */

		/* irq number is run-time assigned */

		.mode = SPI_CS_HIGH,

		.mode = SPI_CS_HIGH,
@@ -406,7 +409,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { 
		.modalias	= "l4f00242t03",

		.modalias	= "l4f00242t03",

		.max_speed_hz	= 5000000,

		.max_speed_hz	= 5000000,

		.bus_num	= 0,

		.bus_num	= 0,

		.chip_select	= 0, /* SS2 */

		.chip_select	= 2, /* SS2 */

		.platform_data	= &mx31_3ds_l4f00242t03_pdata,

		.platform_data	= &mx31_3ds_l4f00242t03_pdata,

	},

	},

};

};

arch/arm/mach-imx/mach-mx31moboard.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -296,14 +296,14 @@ static struct spi_board_info moboard_spi_board_info[] __initdata = { 
		/* irq number is run-time assigned */

		/* irq number is run-time assigned */

		.max_speed_hz = 300000,

		.max_speed_hz = 300000,

		.bus_num = 1,

		.bus_num = 1,

		.chip_select = 0,

		.chip_select = 1,

		.platform_data = &moboard_pmic,

		.platform_data = &moboard_pmic,

		.mode = SPI_CS_HIGH,

		.mode = SPI_CS_HIGH,

	},

	},

};

};





static int moboard_spi2_cs[] = {

static int moboard_spi2_cs[] = {

	MXC_SPI_CS(1),

	MXC_SPI_CS(0), MXC_SPI_CS(1),

};

};





static const struct spi_imx_master moboard_spi2_pdata __initconst = {

static const struct spi_imx_master moboard_spi2_pdata __initconst = {

arch/arm/mach-imx/mach-pcm037_eet.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -50,13 +50,13 @@ static struct spi_board_info pcm037_spi_dev[] = { 
		.modalias	= "dac124s085",

		.modalias	= "dac124s085",

		.max_speed_hz	= 400000,

		.max_speed_hz	= 400000,

		.bus_num	= 0,

		.bus_num	= 0,

		.chip_select	= 0,		/* Index in pcm037_spi1_cs[] */

		.chip_select	= 1,		/* Index in pcm037_spi1_cs[] */

		.mode		= SPI_CPHA,

		.mode		= SPI_CPHA,

	},

	},

};

};





/* Platform Data for MXC CSPI */

/* Platform Data for MXC CSPI */

static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};

static int pcm037_spi1_cs[] = { MXC_SPI_CS(0), MXC_SPI_CS(1), };





static const struct spi_imx_master pcm037_spi1_pdata __initconst = {

static const struct spi_imx_master pcm037_spi1_pdata __initconst = {

	.chipselect = pcm037_spi1_cs,

	.chipselect = pcm037_spi1_cs,

arch/arm/mach-imx/mmdc.c

+19 −1
Original line number Original line Diff line number Diff line 
/*

/*

 * Copyright 2017 NXP

 * Copyright 2011,2016 Freescale Semiconductor, Inc.

 * Copyright 2011,2016 Freescale Semiconductor, Inc.

 * Copyright 2011 Linaro Ltd.

 * Copyright 2011 Linaro Ltd.

 *

 *
@@ -47,6 +48,7 @@ 
#define PROFILE_SEL		0x10

#define PROFILE_SEL		0x10





#define MMDC_MADPCR0	0x410

#define MMDC_MADPCR0	0x410

#define MMDC_MADPCR1	0x414

#define MMDC_MADPSR0	0x418

#define MMDC_MADPSR0	0x418

#define MMDC_MADPSR1	0x41C

#define MMDC_MADPSR1	0x41C

#define MMDC_MADPSR2	0x420

#define MMDC_MADPSR2	0x420
@@ -57,6 +59,7 @@ 
#define MMDC_NUM_COUNTERS	6

#define MMDC_NUM_COUNTERS	6





#define MMDC_FLAG_PROFILE_SEL	0x1

#define MMDC_FLAG_PROFILE_SEL	0x1

#define MMDC_PRF_AXI_ID_CLEAR	0x0





#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)

#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
@@ -87,7 +90,7 @@ static DEFINE_IDA(mmdc_ida); 
PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")

PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")

PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")

PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")

PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")

PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")

PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "config=0x03")

PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")

PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")

PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")

PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");

PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");

PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");

PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
@@ -161,8 +164,11 @@ static struct attribute_group mmdc_pmu_events_attr_group = { 
};

};





PMU_FORMAT_ATTR(event, "config:0-63");

PMU_FORMAT_ATTR(event, "config:0-63");

PMU_FORMAT_ATTR(axi_id, "config1:0-63");



static struct attribute *mmdc_pmu_format_attrs[] = {

static struct attribute *mmdc_pmu_format_attrs[] = {

	&format_attr_event.attr,

	&format_attr_event.attr,

	&format_attr_axi_id.attr,

	NULL,

	NULL,

};

};
@@ -345,6 +351,14 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags) 




	writel(DBG_RST, reg);

	writel(DBG_RST, reg);





	/*

	 * Write the AXI id parameter to MADPCR1.

	 */

	val = event->attr.config1;

	reg = mmdc_base + MMDC_MADPCR1;

	writel(val, reg);



	reg = mmdc_base + MMDC_MADPCR0;

	val = DBG_EN;

	val = DBG_EN;

	if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)

	if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)

		val |= PROFILE_SEL;

		val |= PROFILE_SEL;
@@ -382,6 +396,10 @@ static void mmdc_pmu_event_stop(struct perf_event *event, int flags) 
	reg = mmdc_base + MMDC_MADPCR0;

	reg = mmdc_base + MMDC_MADPCR0;





	writel(PRF_FRZ, reg);

	writel(PRF_FRZ, reg);



	reg = mmdc_base + MMDC_MADPCR1;

	writel(MMDC_PRF_AXI_ID_CLEAR, reg);



	mmdc_pmu_event_update(event);

	mmdc_pmu_event_update(event);

}

}