Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit aad941d5 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Always use crtc_ timings when dealing with adjustead_mode 



The adjustead_mode crtc_ timings are what we will program into the hardware,
so it's those timings we should be looking practically everywhere.

The normal and crtc_ timings should differ only when stere doubling is
used. In that case the normal timings are the orignal non-doubled
timigns, and crtc_ timings are the doubled timings used by the hardware.

The only case where we continue to look at the normal timings is when we
pass the adjusted_mode to drm_match_{cea,hdmi}_mode() to find the VIC.
drm_edid keeps the modes aronund in the non-double form only, so it
needs the non-double timings to match against.

Done with sed
's/adjusted_mode->\([vhVH]\)/adjusted_mode->crtc_\1/g'
's/adjusted_mode->clock/adjusted_mode->crtc_clock/g'
with a manual s/VDisplay/vdisplay/ within the comment in intel_dvo.c

v2: Update due to intel_dsi.c changes

Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5e7234c9

drivers/gpu/drm/i915/dvo_ivch.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -414,16 +414,16 @@ static void ivch_mode_set(struct intel_dvo_device *dvo, 
	vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |

	vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |

		VR40_HORIZONTAL_INTERP_ENABLE);

		VR40_HORIZONTAL_INTERP_ENABLE);





	if (mode->hdisplay != adjusted_mode->hdisplay ||

	if (mode->hdisplay != adjusted_mode->crtc_hdisplay ||

	    mode->vdisplay != adjusted_mode->vdisplay) {

	    mode->vdisplay != adjusted_mode->crtc_vdisplay) {

		uint16_t x_ratio, y_ratio;

		uint16_t x_ratio, y_ratio;





		vr01 |= VR01_PANEL_FIT_ENABLE;

		vr01 |= VR01_PANEL_FIT_ENABLE;

		vr40 |= VR40_CLOCK_GATING_ENABLE;

		vr40 |= VR40_CLOCK_GATING_ENABLE;

		x_ratio = (((mode->hdisplay - 1) << 16) /

		x_ratio = (((mode->hdisplay - 1) << 16) /

			   (adjusted_mode->hdisplay - 1)) >> 2;

			   (adjusted_mode->crtc_hdisplay - 1)) >> 2;

		y_ratio = (((mode->vdisplay - 1) << 16) /

		y_ratio = (((mode->vdisplay - 1) << 16) /

			   (adjusted_mode->vdisplay - 1)) >> 2;

			   (adjusted_mode->crtc_vdisplay - 1)) >> 2;

		ivch_write(dvo, VR42, x_ratio);

		ivch_write(dvo, VR42, x_ratio);

		ivch_write(dvo, VR41, y_ratio);

		ivch_write(dvo, VR41, y_ratio);

	} else {

	} else {

drivers/gpu/drm/i915/intel_audio.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -74,13 +74,13 @@ static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted 
	int i;

	int i;





	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {

	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {

		if (adjusted_mode->clock == hdmi_audio_clock[i].clock)

		if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)

			break;

			break;

	}

	}





	if (i == ARRAY_SIZE(hdmi_audio_clock)) {

	if (i == ARRAY_SIZE(hdmi_audio_clock)) {

		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",

		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",

			      adjusted_mode->clock);

			      adjusted_mode->crtc_clock);

		i = 1;

		i = 1;

	}

	}

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -4400,7 +4400,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state) 
	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,

	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,

		&state->scaler_state.scaler_id, DRM_ROTATE_0,

		&state->scaler_state.scaler_id, DRM_ROTATE_0,

		state->pipe_src_w, state->pipe_src_h,

		state->pipe_src_w, state->pipe_src_h,

		adjusted_mode->hdisplay, adjusted_mode->vdisplay);

		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);

}

}





/**

/**
@@ -6593,7 +6593,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, 
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.

	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.

	 */

	 */

	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&

	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&

		adjusted_mode->hsync_start == adjusted_mode->hdisplay)

		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)

		return -EINVAL;

		return -EINVAL;





	if (HAS_IPS(dev))

	if (HAS_IPS(dev))

drivers/gpu/drm/i915/intel_dp_mst.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -78,7 +78,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 
		return false;

		return false;

	}

	}





	mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);

	mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);





	pipe_config->pbn = mst_pbn;

	pipe_config->pbn = mst_pbn;

	slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn);

	slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn);

drivers/gpu/drm/i915/intel_dsi.c

+15 −15
Original line number Original line Diff line number Diff line
@@ -710,10 +710,10 @@ static void set_dsi_timings(struct drm_encoder *encoder, 




	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;

	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;





	hactive = adjusted_mode->hdisplay;

	hactive = adjusted_mode->crtc_hdisplay;

	hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;

	hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;

	hsync = adjusted_mode->hsync_end - adjusted_mode->hsync_start;

	hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;

	hbp = adjusted_mode->htotal - adjusted_mode->hsync_end;

	hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;





	if (intel_dsi->dual_link) {

	if (intel_dsi->dual_link) {

		hactive /= 2;

		hactive /= 2;
@@ -724,9 +724,9 @@ static void set_dsi_timings(struct drm_encoder *encoder, 
		hbp /= 2;

		hbp /= 2;

	}

	}





	vfp = adjusted_mode->vsync_start - adjusted_mode->vdisplay;

	vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;

	vsync = adjusted_mode->vsync_end - adjusted_mode->vsync_start;

	vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;

	vbp = adjusted_mode->vtotal - adjusted_mode->vsync_end;

	vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;





	/* horizontal values are in terms of high speed byte clock */

	/* horizontal values are in terms of high speed byte clock */

	hactive = txbyteclkhs(hactive, bpp, lane_count,

	hactive = txbyteclkhs(hactive, bpp, lane_count,
@@ -745,11 +745,11 @@ static void set_dsi_timings(struct drm_encoder *encoder, 
			 * whereas these values should be based on resolution.

			 * whereas these values should be based on resolution.

			 */

			 */

			I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),

			I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),

				   adjusted_mode->hdisplay);

				   adjusted_mode->crtc_hdisplay);

			I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),

			I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),

				   adjusted_mode->vdisplay);

				   adjusted_mode->crtc_vdisplay);

			I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),

			I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),

				   adjusted_mode->vtotal);

				   adjusted_mode->crtc_vtotal);

		}

		}





		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);

		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
@@ -782,7 +782,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) 




	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));

	DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));





	mode_hdisplay = adjusted_mode->hdisplay;

	mode_hdisplay = adjusted_mode->crtc_hdisplay;





	if (intel_dsi->dual_link) {

	if (intel_dsi->dual_link) {

		mode_hdisplay /= 2;

		mode_hdisplay /= 2;
@@ -832,7 +832,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) 
		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);

		I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);





		I915_WRITE(MIPI_DPI_RESOLUTION(port),

		I915_WRITE(MIPI_DPI_RESOLUTION(port),

			adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |

			adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |

			mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);

			mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);

	}

	}
@@ -878,13 +878,13 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) 
		if (is_vid_mode(intel_dsi) &&

		if (is_vid_mode(intel_dsi) &&

			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {

			intel_dsi->video_mode_format == VIDEO_MODE_BURST) {

			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),

			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),

				txbyteclkhs(adjusted_mode->htotal, bpp,

				txbyteclkhs(adjusted_mode->crtc_htotal, bpp,

					    intel_dsi->lane_count,

					    intel_dsi->lane_count,

					    intel_dsi->burst_mode_ratio) + 1);

					    intel_dsi->burst_mode_ratio) + 1);

		} else {

		} else {

			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),

			I915_WRITE(MIPI_HS_TX_TIMEOUT(port),

				txbyteclkhs(adjusted_mode->vtotal *

				txbyteclkhs(adjusted_mode->crtc_vtotal *

					    adjusted_mode->htotal,

					    adjusted_mode->crtc_htotal,

					    bpp, intel_dsi->lane_count,

					    bpp, intel_dsi->lane_count,

					    intel_dsi->burst_mode_ratio) + 1);

					    intel_dsi->burst_mode_ratio) + 1);

		}

		}