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Commit aaa65d77 authored by Gabriel FERNANDEZ's avatar Gabriel FERNANDEZ Committed by Mike Turquette
Browse files

clk: st: STiH407: Support for clockgenA9 



The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarOlivier Bideau <olivier.bideau@st.com>
Acked-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 58de9b8e

drivers/clk/st/clkgen-pll.c

+16 −0
Original line number Diff line number Diff line
@@ -216,6 +216,18 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = { 
	.ops		= &stm_pll3200c32_ops,

};



static const struct clkgen_pll_data st_pll3200c32_407_a9 = {

	/* 407 A9 */

	.pdn_status	= CLKGEN_FIELD(0x1a8,	0x1,			0),

	.locked_status	= CLKGEN_FIELD(0x87c,	0x1,			0),

	.ndiv		= CLKGEN_FIELD(0x1b0,	C32_NDIV_MASK,		0),

	.idf		= CLKGEN_FIELD(0x1a8,	C32_IDF_MASK,		25),

	.num_odfs = 1,

	.odf		= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK,		8) },

	.odf_gate	= { CLKGEN_FIELD(0x1ac, 0x1,			28) },

	.ops		= &stm_pll3200c32_ops,

};



/**

 * DOC: Clock Generated by PLL, rate set and enabled by bootloader

 *
@@ -618,6 +630,10 @@ static struct of_device_id c32_pll_of_match[] = { 
		.compatible = "st,stih407-plls-c32-c0_1",

		.data = &st_pll3200c32_407_c0_1,

	},

	{

		.compatible = "st,stih407-plls-c32-a9",

		.data = &st_pll3200c32_407_a9,

	},

	{}

};