Loading drivers/gpu/drm/nouveau/nv50_graph.c +8 −2 Original line number Diff line number Diff line Loading @@ -425,8 +425,6 @@ nv50_graph_register(struct drm_device *dev) NVOBJ_CLASS(dev, 0x0030, GR); /* null */ NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */ NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */ NVOBJ_CLASS(dev, 0x50c0, GR); /* compute */ NVOBJ_CLASS(dev, 0x85c0, GR); /* compute (nva3, nva5, nva8) */ /* tesla */ if (dev_priv->chipset == 0x50) Loading @@ -452,6 +450,14 @@ nv50_graph_register(struct drm_device *dev) } } /* compute */ if (dev_priv->chipset <= 0xa0 || dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) NVOBJ_CLASS(dev, 0x50c0, GR); else NVOBJ_CLASS(dev, 0x85c0, GR); dev_priv->engine.graph.registered = true; return 0; } Loading Loading
drivers/gpu/drm/nouveau/nv50_graph.c +8 −2 Original line number Diff line number Diff line Loading @@ -425,8 +425,6 @@ nv50_graph_register(struct drm_device *dev) NVOBJ_CLASS(dev, 0x0030, GR); /* null */ NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */ NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */ NVOBJ_CLASS(dev, 0x50c0, GR); /* compute */ NVOBJ_CLASS(dev, 0x85c0, GR); /* compute (nva3, nva5, nva8) */ /* tesla */ if (dev_priv->chipset == 0x50) Loading @@ -452,6 +450,14 @@ nv50_graph_register(struct drm_device *dev) } } /* compute */ if (dev_priv->chipset <= 0xa0 || dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) NVOBJ_CLASS(dev, 0x50c0, GR); else NVOBJ_CLASS(dev, 0x85c0, GR); dev_priv->engine.graph.registered = true; return 0; } Loading