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Commit aa08192a authored by Aniruddha Banerjee's avatar Aniruddha Banerjee Committed by Marc Zyngier
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irqchip/gic: Take lock when updating irq type 



Most MMIO GIC register accesses use a 1-hot bit scheme that
avoids requiring any form of locking. This isn't true for the
GICD_ICFGRn registers, which require a RMW sequence.

Unfortunately, we seem to be missing a lock for these particular
accesses, which could result in a race condition if changing the
trigger type on any two interrupts within the same set of 16
interrupts (and thus controlled by the same CFGR register).

Introduce a private lock in the GIC common comde for this
particular case, making it cover both GIC implementations
in one go.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarAniruddha Banerjee <aniruddhab@nvidia.com>
[maz: updated changelog]
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent d01d3274

drivers/irqchip/irq-gic-common.c

+8 −1
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 


#include "irq-gic-common.h"



static DEFINE_RAW_SPINLOCK(irq_controller_lock);



static const struct gic_kvm_info *gic_kvm_info;



const struct gic_kvm_info *gic_get_kvm_info(void)
@@ -53,11 +55,13 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
	u32 confoff = (irq / 16) * 4;

	u32 val, oldval;

	int ret = 0;

	unsigned long flags;



	/*

	 * Read current configuration register, and insert the config

	 * for "irq", depending on "type".

	 */

	raw_spin_lock_irqsave(&irq_controller_lock, flags);

	val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);

	if (type & IRQ_TYPE_LEVEL_MASK)

		val &= ~confmask;
@@ -65,8 +69,10 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
		val |= confmask;



	/* If the current configuration is the same, then we are done */

	if (val == oldval)

	if (val == oldval) {

		raw_spin_unlock_irqrestore(&irq_controller_lock, flags);

		return 0;

	}



	/*

	 * Write back the new configuration, and possibly re-enable
@@ -84,6 +90,7 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
			pr_warn("GIC: PPI%d is secure or misconfigured\n",

				irq - 16);

	}

	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);



	if (sync_access)

		sync_access();