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Commit a9abb475 authored by Luke Starrett's avatar Luke Starrett Committed by Florian Fainelli
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arm64: dts: NS2 secondary core enablement via PSCI 



Declare PSCI-1.0 node and enable CPU_ON method via PSCI.  Spin-table
memreserve has been removed as well as syscon based reset, as PSCI-1.0
expects reset implementation in firmware.

Signed-off-by: default avatarLuke Starrett <luke.starrett@broadcom.com>
Acked-by: default avatarScott Branden <scott.branden@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent d69dbd9f

arch/arm64/boot/dts/broadcom/ns2.dtsi

+9 −22
Original line number Diff line number Diff line
@@ -33,8 +33,6 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/bcm-ns2.h>



/memreserve/ 0x84b00000 0x00000008;



/ {

	compatible = "brcm,ns2";

	interrupt-parent = <&gic>;
@@ -49,8 +47,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 0>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			enable-method = "psci";

			next-level-cache = <&CLUSTER0_L2>;

		};
@@ -58,8 +55,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 1>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			enable-method = "psci";

			next-level-cache = <&CLUSTER0_L2>;

		};
@@ -67,8 +63,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 2>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			enable-method = "psci";

			next-level-cache = <&CLUSTER0_L2>;

		};
@@ -76,8 +71,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0 3>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			enable-method = "psci";

			next-level-cache = <&CLUSTER0_L2>;

		};
@@ -86,6 +80,11 @@ 
		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
@@ -252,18 +251,6 @@ 
			mmu-masters;

		};



		crmu: crmu@65024000 {

			compatible = "syscon";

			reg = <0x65024000 0x100>;

		};



		reboot@65024000 {

			compatible ="syscon-reboot";

			regmap = <&crmu>;

			offset = <0x90>;

			mask = <0xfffffffd>;

		};



		gic: interrupt-controller@65210000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;